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Add some more DWARF ARM register numbers to the DWARF CFI register maps

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R=jimb at https://breakpad.appspot.com/418002/

git-svn-id: http://google-breakpad.googlecode.com/svn/trunk@988 4c0a9323-5329-0410-9bdc-e9ce6186880e
This commit is contained in:
ted.mielczarek 2012-07-18 18:13:29 +00:00
parent 4116671cbf
commit 72542b052d
2 changed files with 28 additions and 5 deletions
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15
src/common/dwarf_cfi_to_module.cc
View file

@ -84,12 +84,22 @@ vector<string> DwarfCFIToModule::RegisterNames::X86_64() {
return MakeVector(names, sizeof(names) / sizeof(names[0])); return MakeVector(names, sizeof(names) / sizeof(names[0]));
} }
// Per ARM IHI 0040A, section 3.1
vector<string> DwarfCFIToModule::RegisterNames::ARM() { vector<string> DwarfCFIToModule::RegisterNames::ARM() {
static const char *const names[] = { static const char *const names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"fps", "cpsr" "fps", "cpsr", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7"
}; };
return MakeVector(names, sizeof(names) / sizeof(names[0])); return MakeVector(names, sizeof(names) / sizeof(names[0]));
@ -132,7 +142,8 @@ string DwarfCFIToModule::RegisterName(int i) {
if (reg == return_address_) if (reg == return_address_)
return ra_name_; return ra_name_;
if (reg < register_names_.size()) // Ensure that a non-empty name exists for this register value.
if (reg < register_names_.size() && !register_names_[reg].empty())
return register_names_[reg]; return register_names_[reg];
reporter_->UnnamedRegister(entry_offset_, reg); reporter_->UnnamedRegister(entry_offset_, reg);

18
src/common/dwarf_cfi_to_module_unittest.cc
View file

@ -69,6 +69,7 @@ struct DwarfCFIToModuleFixture {
register_names.push_back("reg7"); register_names.push_back("reg7");
register_names.push_back("sp"); register_names.push_back("sp");
register_names.push_back("pc"); register_names.push_back("pc");
register_names.push_back("");
EXPECT_CALL(reporter, UnnamedRegister(_, _)).Times(0); EXPECT_CALL(reporter, UnnamedRegister(_, _)).Times(0);
EXPECT_CALL(reporter, UndefinedNotSupported(_, _)).Times(0); EXPECT_CALL(reporter, UndefinedNotSupported(_, _)).Times(0);
@ -140,6 +141,17 @@ TEST_F(Rule, UndefinedRule) {
EXPECT_EQ(0U, entries[0]->rule_changes.size()); EXPECT_EQ(0U, entries[0]->rule_changes.size());
} }
TEST_F(Rule, RegisterWithEmptyName) {
EXPECT_CALL(reporter, UnnamedRegister(_, 10));
EXPECT_CALL(reporter, UndefinedNotSupported(_, "unnamed_register10"));
StartEntry();
ASSERT_TRUE(handler.UndefinedRule(entry_address, 10));
ASSERT_TRUE(handler.End());
CheckEntry();
EXPECT_EQ(0U, entries[0]->initial_rules.size());
EXPECT_EQ(0U, entries[0]->rule_changes.size());
}
TEST_F(Rule, SameValueRule) { TEST_F(Rule, SameValueRule) {
StartEntry(); StartEntry();
ASSERT_TRUE(handler.SameValueRule(entry_address, 6)); ASSERT_TRUE(handler.SameValueRule(entry_address, 6));
@ -178,17 +190,17 @@ TEST_F(Rule, OffsetRuleNegative) {
TEST_F(Rule, ValOffsetRule) { TEST_F(Rule, ValOffsetRule) {
// Use an unnamed register number, to exercise that branch of RegisterName. // Use an unnamed register number, to exercise that branch of RegisterName.
EXPECT_CALL(reporter, UnnamedRegister(_, 10)); EXPECT_CALL(reporter, UnnamedRegister(_, 11));
StartEntry(); StartEntry();
ASSERT_TRUE(handler.ValOffsetRule(entry_address + 0x5ab7, ASSERT_TRUE(handler.ValOffsetRule(entry_address + 0x5ab7,
DwarfCFIToModule::kCFARegister, DwarfCFIToModule::kCFARegister,
10, 61812979)); 11, 61812979));
ASSERT_TRUE(handler.End()); ASSERT_TRUE(handler.End());
CheckEntry(); CheckEntry();
EXPECT_EQ(0U, entries[0]->initial_rules.size()); EXPECT_EQ(0U, entries[0]->initial_rules.size());
Module::RuleChangeMap expected_changes; Module::RuleChangeMap expected_changes;
expected_changes[entry_address + 0x5ab7][".cfa"] = expected_changes[entry_address + 0x5ab7][".cfa"] =
"unnamed_register10 61812979 +"; "unnamed_register11 61812979 +";
EXPECT_THAT(entries[0]->rule_changes, ContainerEq(expected_changes)); EXPECT_THAT(entries[0]->rule_changes, ContainerEq(expected_changes));
} }