From f4a3b346f34ab4f3bf39f983b601cadd3fc12312 Mon Sep 17 00:00:00 2001 From: Mark Brand Date: Mon, 8 May 2023 10:35:58 +0200 Subject: [PATCH] [dump_syms][riscv] Update unittest. Change 4505156 changed the RISCV register names, this change adjusts the unittest to match the new names. Bug: 1432426 Change-Id: I0887d8fc11eec63ab6953ea1a136873591e49286 Reviewed-on: https://chromium-review.googlesource.com/c/breakpad/breakpad/+/4507066 Reviewed-by: Joshua Peraza --- src/common/dwarf_cfi_to_module_unittest.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/common/dwarf_cfi_to_module_unittest.cc b/src/common/dwarf_cfi_to_module_unittest.cc index b407edd0..52653ec6 100644 --- a/src/common/dwarf_cfi_to_module_unittest.cc +++ b/src/common/dwarf_cfi_to_module_unittest.cc @@ -311,8 +311,8 @@ TEST(RegisterNames, X86_64) { TEST(RegisterNames, RISCV) { vector names = DwarfCFIToModule::RegisterNames::RISCV(); - EXPECT_EQ("x0", names[0]); - EXPECT_EQ("x31", names[31]); + EXPECT_EQ("pc", names[0]); + EXPECT_EQ("t6", names[31]); EXPECT_EQ("f0", names[32]); EXPECT_EQ("f31", names[63]); EXPECT_EQ("v0", names[96]);