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https://github.com/yuzu-emu/sirit
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Add OpStore
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2 changed files with 28 additions and 0 deletions
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@ -204,11 +204,19 @@ class Module {
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Ref Load(Ref result_type, Ref pointer,
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Ref Load(Ref result_type, Ref pointer,
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std::optional<spv::MemoryAccessMask> memory_access = {});
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std::optional<spv::MemoryAccessMask> memory_access = {});
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/// Store through a pointer.
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Ref Store(Ref pointer, Ref object,
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std::optional<spv::MemoryAccessMask> memory_access = {});
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/// Create a pointer into a composite object that can be used with OpLoad
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/// Create a pointer into a composite object that can be used with OpLoad
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/// and OpStore.
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/// and OpStore.
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Ref AccessChain(Ref result_type, Ref base,
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Ref AccessChain(Ref result_type, Ref base,
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const std::vector<Ref>& indexes = {});
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const std::vector<Ref>& indexes = {});
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/// Make a copy of a composite object, while modifying one part of it.
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Ref CompositeInsert(Ref result_type, Ref object, Ref composite,
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const std::vector<Literal>& indexes = {});
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// Annotation
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// Annotation
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/// Add a decoration to target.
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/// Add a decoration to target.
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@ -30,6 +30,17 @@ Ref Module::Load(Ref result_type, Ref pointer,
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return AddCode(op);
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return AddCode(op);
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}
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}
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Ref Module::Store(Ref pointer, Ref object,
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std::optional<spv::MemoryAccessMask> memory_access) {
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auto op{new Op(spv::Op::OpStore)};
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op->Add(pointer);
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op->Add(object);
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if (memory_access) {
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AddEnum(op, *memory_access);
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}
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return AddCode(op);
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}
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Ref Module::AccessChain(Ref result_type, Ref base,
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Ref Module::AccessChain(Ref result_type, Ref base,
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const std::vector<Ref>& indexes) {
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const std::vector<Ref>& indexes) {
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assert(indexes.size() > 0);
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assert(indexes.size() > 0);
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@ -39,4 +50,13 @@ Ref Module::AccessChain(Ref result_type, Ref base,
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return AddCode(op);
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return AddCode(op);
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}
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}
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Ref Module::CompositeInsert(Ref result_type, Ref object, Ref composite,
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const std::vector<Literal>& indexes) {
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auto op{new Op(spv::Op::OpCompositeInsert, bound++, result_type)};
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op->Add(object);
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op->Add(composite);
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op->Add(indexes);
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return AddCode(op);
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}
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} // namespace Sirit
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} // namespace Sirit
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