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https://github.com/yuzu-emu/sirit
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Add OpIAdd and OpBitwiseAnd
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15a4d3c0d4
commit
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3 changed files with 24 additions and 6 deletions
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@ -262,11 +262,18 @@ class Module {
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/// The least-significant bits will be zero filled.
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Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
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/// Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
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/// Operand 1 or Operand 2 are 0.
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Id OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2);
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// Arithmetic
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/// Unsigned-integer division of Operand 1 divided by Operand 2.
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Id OpUDiv(Id result_type, Id operand_1, Id operand_2);
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/// Integer addition of Operand 1 and Operand 2.
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Id OpIAdd(Id result_type, Id operand_1, Id operand_2);
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private:
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Id AddCode(std::unique_ptr<Op> op);
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@ -11,11 +11,15 @@
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namespace Sirit {
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Id Module::OpUDiv(Id result_type, Id operand_1, Id operand_2) {
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auto op{std::make_unique<Op>(spv::Op::OpUDiv, bound++, result_type)};
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op->Add(operand_1);
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op->Add(operand_2);
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return AddCode(std::move(op));
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}
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#define DEFINE_BINARY(funcname, opcode) \
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Id Module::funcname(Id result_type, Id operand_1, Id operand_2) { \
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auto op{std::make_unique<Op>(opcode, bound++, result_type)}; \
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op->Add(operand_1); \
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op->Add(operand_2); \
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return AddCode(std::move(op)); \
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}
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DEFINE_BINARY(OpUDiv, spv::Op::OpUDiv)
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DEFINE_BINARY(OpIAdd, spv::Op::OpIAdd)
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} // namespace Sirit
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@ -35,4 +35,11 @@ Id Module::OpShiftLeftLogical(Id result_type, Id base, Id shift) {
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return AddCode(std::move(op));
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}
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Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
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auto op{std::make_unique<Op>(spv::Op::OpBitwiseAnd, bound++, result_type)};
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op->Add(operand_1);
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op->Add(operand_2);
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return AddCode(std::move(op));
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}
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} // namespace Sirit
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