mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-24 17:18:08 +00:00
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
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/*
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* QEMU RISC-V Spike Board
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides a RISC-V Board with the following devices:
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*
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* 0) HTIF Console and Poweroff
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* 1) CLINT (Timer and IPI)
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/riscv/spike.h"
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#include "hw/boards.h"
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#include "exec/address-spaces.h"
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static int spike_v1_10_0_board_init(struct uc_struct *uc, MachineState *machine)
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{
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uc->cpu = cpu_create(uc, machine->cpu_type);
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if (uc->cpu == NULL) {
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fprintf(stderr, "Unable to make CPU definition\n");
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return -1;
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}
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return 0;
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}
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static void spike_v1_10_0_machine_init(struct uc_struct *uc, MachineClass *mc)
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{
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mc->init = spike_v1_10_0_board_init;
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mc->max_cpus = 1;
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mc->is_default = 1;
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// Unicorn: instead of using SPIKE_V1_10_0_CPU like qemu,
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// we use specific values to allow selection of the
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// preferred bitness of the architecture.
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if (uc->mode == UC_MODE_RISCV32) {
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mc->default_cpu_type = TYPE_RISCV_CPU_RV32GCSU_V1_10_0;
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} else {
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mc->default_cpu_type = TYPE_RISCV_CPU_RV64GCSU_V1_10_0;
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}
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mc->arch = UC_ARCH_RISCV;
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}
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DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
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