From 0150ca24b1770ada58377817bc9c2c8b210a4da3 Mon Sep 17 00:00:00 2001 From: feliam Date: Thu, 9 Mar 2017 11:28:03 -0300 Subject: [PATCH] Add support for ARM application flags - APSR register (#776) --- bindings/python/sample_arm.py | 3 ++- qemu/target-arm/unicorn_arm.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/python/sample_arm.py b/bindings/python/sample_arm.py index 402ba57a..5fae6b6b 100755 --- a/bindings/python/sample_arm.py +++ b/bindings/python/sample_arm.py @@ -41,7 +41,8 @@ def test_arm(): mu.reg_write(UC_ARM_REG_R0, 0x1234) mu.reg_write(UC_ARM_REG_R2, 0x6789) mu.reg_write(UC_ARM_REG_R3, 0x3333) - + mu.reg_write(UC_ARM_REG_APSR, 0xFFFFFFFF) #All application flags turned on + # tracing all basic blocks with customized callback mu.hook_add(UC_HOOK_BLOCK, hook_block) diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c index 7bb985e2..1dffb432 100644 --- a/qemu/target-arm/unicorn_arm.c +++ b/qemu/target-arm/unicorn_arm.c @@ -62,6 +62,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun *(float64 *)value = ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0]; else { switch(regid) { + case UC_ARM_REG_APSR: + *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV; + break; case UC_ARM_REG_CPSR: *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env); break; @@ -107,6 +110,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0] = *(float64 *)value; else { switch(regid) { + case UC_ARM_REG_APSR: + cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, CPSR_NZCV); + break; case UC_ARM_REG_CPSR: cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, ~0); break;