From 0640b35943be950e1b023531b903638ee11107a4 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Thu, 19 Jan 2017 13:07:28 +0800 Subject: [PATCH] mips: remove qemu/hw/mips/mips_int.c --- qemu/header_gen.py | 1 - qemu/hw/mips/Makefile.objs | 2 +- qemu/hw/mips/mips_int.c | 82 ------------------------------------ qemu/mips.h | 1 - qemu/mips64.h | 1 - qemu/mips64el.h | 1 - qemu/mipsel.h | 1 - qemu/target-mips/op_helper.c | 4 +- 8 files changed, 4 insertions(+), 89 deletions(-) delete mode 100644 qemu/hw/mips/mips_int.c diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 4496ff0c..97250191 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3078,7 +3078,6 @@ mips_symbols = ( 'cpu_mips_clock_init', 'mips_machine_init', 'cpu_mips_irq_init_cpu', - 'cpu_mips_soft_irq', 'cpu_mips_kseg0_to_phys', 'cpu_mips_phys_to_kseg0', 'cpu_mips_kvm_um_phys_to_kseg0', diff --git a/qemu/hw/mips/Makefile.objs b/qemu/hw/mips/Makefile.objs index 1e6faec4..910e23b0 100644 --- a/qemu/hw/mips/Makefile.objs +++ b/qemu/hw/mips/Makefile.objs @@ -1,2 +1,2 @@ obj-y += mips_r4k.o -obj-y += addr.o cputimer.o mips_int.o +obj-y += addr.o cputimer.o diff --git a/qemu/hw/mips/mips_int.c b/qemu/hw/mips/mips_int.c deleted file mode 100644 index c57c8f35..00000000 --- a/qemu/hw/mips/mips_int.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * QEMU MIPS interrupt support - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "hw/hw.h" -#include "hw/mips/cpudevs.h" -#include "cpu.h" -//#include "kvm_mips.h" - -#if 0 -static void cpu_mips_irq_request(void *opaque, int irq, int level) -{ - MIPSCPU *cpu = opaque; - CPUMIPSState *env = &cpu->env; - CPUState *cs = CPU(cpu); - - if (irq < 0 || irq > 7) - return; - - if (level) { - env->CP0_Cause |= 1 << (irq + CP0Ca_IP); - - if (kvm_enabled() && irq == 2) { - kvm_mips_set_interrupt(cpu, irq, level); - } - - } else { - env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); - if (kvm_enabled() && irq == 2) { - kvm_mips_set_interrupt(cpu, irq, level); - } - } - - if (env->CP0_Cause & CP0Ca_IP_mask) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} -#endif - -void cpu_mips_irq_init_cpu(CPUMIPSState *env) -{ -#if 0 - qemu_irq *qi; - int i; - - qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8); - for (i = 0; i < 8; i++) { - env->irq[i] = qi[i]; - } -#endif -} - -void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) -{ -#if 0 - if (irq < 0 || irq > 2) { - return; - } - - qemu_set_irq(env->irq[irq], level); -#endif -} diff --git a/qemu/mips.h b/qemu/mips.h index ca90aa90..d42a7644 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3069,7 +3069,6 @@ #define cpu_mips_clock_init cpu_mips_clock_init_mips #define mips_machine_init mips_machine_init_mips #define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips -#define cpu_mips_soft_irq cpu_mips_soft_irq_mips #define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips #define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips #define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 1a8a3c1a..d48af1cd 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3069,7 +3069,6 @@ #define cpu_mips_clock_init cpu_mips_clock_init_mips64 #define mips_machine_init mips_machine_init_mips64 #define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips64 -#define cpu_mips_soft_irq cpu_mips_soft_irq_mips64 #define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64 #define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64 #define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index ec09fd98..144f348e 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3069,7 +3069,6 @@ #define cpu_mips_clock_init cpu_mips_clock_init_mips64el #define mips_machine_init mips_machine_init_mips64el #define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips64el -#define cpu_mips_soft_irq cpu_mips_soft_irq_mips64el #define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64el #define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64el #define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index e4833da3..0b68376b 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3069,7 +3069,6 @@ #define cpu_mips_clock_init cpu_mips_clock_init_mipsel #define mips_machine_init mips_machine_init_mipsel #define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mipsel -#define cpu_mips_soft_irq cpu_mips_soft_irq_mipsel #define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mipsel #define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mipsel #define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mipsel diff --git a/qemu/target-mips/op_helper.c b/qemu/target-mips/op_helper.c index e7b16cae..6e142390 100644 --- a/qemu/target-mips/op_helper.c +++ b/qemu/target-mips/op_helper.c @@ -1478,7 +1478,6 @@ static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) { uint32_t mask = 0x00C00300; uint32_t old = cpu->CP0_Cause; - int i; if (cpu->insn_flags & ISA_MIPS32R2) { mask |= 1 << CP0Ca_DC; @@ -1497,12 +1496,15 @@ static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) } } +#if 0 + int i; /* Set/reset software interrupts */ for (i = 0 ; i < 2 ; i++) { if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) { cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i))); } } +#endif } void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)