mirrors-yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn synced 2024-11-25 16:25:37 +00:00
Code Issues Projects Releases Packages Wiki Activity

target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2

Browse source 
Use a symbolic constant M_REG_NUM_BANKS for the array size for
registers which are banked by M profile security state, rather
than hardcoding lots of 2s.

Backports commit 4a16724f06ead684a5962477a557c26c677c2729 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 23:07:23 -05:00 committed by Lioncash
parent 9730b2ccf6
commit 09ca9356a3
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 19 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
qemu/target/arm/cpu.h
View file

@ -85,8 +85,11 @@
* accessed via env->registerfield[env->v7m.secure] (whether the security
* extension is implemented or not).
*/
#define M_REG_NS 0
#define M_REG_S 1
enum {
M_REG_NS = 0,
M_REG_S = 1,
M_REG_NUM_BANKS = 2,
};
/* ARM-specific interrupt pending bits. */
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
@ -438,19 +441,19 @@ typedef struct CPUARMState {
uint32_t other_sp;
uint32_t other_ss_msp;
uint32_t other_ss_psp;
uint32_t vecbase[2];
uint32_t basepri[2];
uint32_t control[2];
uint32_t ccr[2]; /* Configuration and Control */
uint32_t cfsr[2]; /* Configurable Fault Status */
uint32_t vecbase[M_REG_NUM_BANKS];
uint32_t basepri[M_REG_NUM_BANKS];
uint32_t control[M_REG_NUM_BANKS];
uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
uint32_t hfsr; /* HardFault Status */
uint32_t dfsr; /* Debug Fault Status Register */
uint32_t mmfar[2]; /* MemManage Fault Address */
uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl[2]; /* MPU_CTRL */
unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
int exception;
uint32_t primask[2];
uint32_t faultmask[2];
uint32_t primask[M_REG_NUM_BANKS];
uint32_t faultmask[M_REG_NUM_BANKS];
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
} v7m;
@ -551,7 +554,7 @@ typedef struct CPUARMState {
uint32_t *drbar;
uint32_t *drsr;
uint32_t *dracr;
uint32_t rnr[2];
uint32_t rnr[M_REG_NUM_BANKS];
} pmsav7;
/* PMSAv8 MPU */
@ -561,10 +564,10 @@ typedef struct CPUARMState {
* pmsav7.rnr (region number register)
* pmsav7_dregion (number of configured regions)
*/
uint32_t *rbar[2];
uint32_t *rlar[2];
uint32_t mair0[2];
uint32_t mair1[2];
uint32_t *rbar[M_REG_NUM_BANKS];
uint32_t *rlar[M_REG_NUM_BANKS];
uint32_t mair0[M_REG_NUM_BANKS];
uint32_t mair1[M_REG_NUM_BANKS];
} pmsav8;
void *nvic;