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target/mips: Use BS_EXCP where interrupts are expected

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Commit e350d8ca3ac7 ("target/mips: optimize indirect branches") made
indirect branches able to directly find the next TB and jump straight to
it without breaking out of translated code and going around the main
execution loop. This breaks the assumption in target/mips/translate.c
that BS_STOP is sufficient to cause pending interrupts to be handled,
since interrupts are only checked in the main loop.

Fix a few of these assumptions by using gen_save_pc to update the saved
PC and using BS_EXCP instead of BS_STOP:

- [D]MFC0 CP0_Count may trigger a timer interrupt which should be
immediately handled.

- [D]MTC0 CP0_Cause may trigger an interrupt (but in fact translation
was only even being stopped in the DMTC0 case).

- [D]MTC0 CP0_<any> when icount is used is assumed could potentially
cause interrupts.

- EI may trigger an interrupt which was pending. I specifically hit
this case when running KVM nested in mipsel-softmmu. A timer
interrupt while the 2nd guest was executing is caught by KVM which
switches back to the normal Linux exception base and re-enables
interrupts with EI. Since the above commit QEMU doesn't leave
translated code until the nested KVM has already restored the KVM
exception base and returned to the 2nd guest, at which point it is
too late to check for pending interrupts and it gets stuck in an
infinite loop of unhandled interrupts.

Something similar was needed for ARM in commit b29fd33db578
("target/arm: use DISAS_EXIT for eret handling").

Backports commit b74cddcbf6063f684725e3f8bca49a68e30cba71 from qemu
This commit is contained in:
James Hogan 2018-03-04 01:32:21 -05:00 committed by Lioncash
parent 4a1ec3bb80
commit 0afa0c8ddc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 34 additions and 13 deletions
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47
qemu/target/mips/translate.c
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@ -5412,8 +5412,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_io_end();
//}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
ctx->bstate = BS_STOP;
after reading count. BS_STOP isn't sufficient, we need to ensure
we break completely out of translated code. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@ -6142,6 +6144,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "Cause";
/* Stop translation as we may have triggered an interrupt. BS_STOP
* isn't sufficient, we need to ensure we break out of translated
* code to check for pending interrupts. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
break;
default:
goto cp0_unimplemented;
@ -6481,7 +6488,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
//if (ctx->tb->cflags & CF_USE_ICOUNT) {
// gen_io_end();
// ctx->bstate = BS_STOP;
// /* BS_STOP isn't sufficient, we need to ensure we break out of
// * translated code to check for pending interrupts. */
// gen_save_pc(ctx, ctx->pc + 4);
// ctx->bstate = BS_EXCP;
//}
return;
@ -6763,8 +6773,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_io_end();
//}
/* Break the TB to be able to take timer interrupts immediately
after reading count. */
ctx->bstate = BS_STOP;
after reading count. BS_STOP isn't sufficient, we need to ensure
we break completely out of translated code. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@ -7482,8 +7494,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
//if (ctx->tb->cflags & CF_USE_ICOUNT) {
// gen_io_end();
//}
/* Stop translation as we may have triggered an intetrupt */
ctx->bstate = BS_STOP;
/* Stop translation as we may have triggered an intetrupt. BS_STOP
* isn't sufficient, we need to ensure we break out of translated
* code to check for pending interrupts. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Cause";
break;
default:
@ -7805,7 +7820,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
//if (ctx->tb->cflags & CF_USE_ICOUNT) {
// gen_io_end();
// ctx->bstate = BS_STOP;
// /* BS_STOP isn't sufficient, we need to ensure we break out of
// * translated code to check for pending interrupts. */
// gen_save_pc(ctx, ctx->pc + 4);
// ctx->bstate = BS_EXCP;
//}
return;
@ -13673,8 +13691,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
save_cpu_state(ctx, 1);
gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rs);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
/* BS_STOP isn't sufficient, we need to ensure we break out
of translated code to check for pending interrupts. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
tcg_temp_free(tcg_ctx, t0);
}
break;
@ -19866,9 +19886,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
save_cpu_state(ctx, 1);
gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
gen_store_gpr(tcg_ctx, t0, rt);
/* Stop translation as we may have switched
the execution mode */
ctx->bstate = BS_STOP;
/* BS_STOP isn't sufficient, we need to ensure we break out
of translated code to check for pending interrupts. */
gen_save_pc(ctx, ctx->pc + 4);
ctx->bstate = BS_EXCP;
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");