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softfloat: Specialize udiv_qrnnd for s390x

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The ISA has a 128/64-bit division instruction.

Backports commit 739df333dc8853ae6578492675a26a601d6be077 from qemu
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Richard Henderson 2018-10-08 11:07:27 -04:00 committed by Lioncash
parent 8de4da1475
commit 0fd568871e
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1 changed files with 6 additions and 0 deletions
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6
qemu/fpu/softfloat-macros.h
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@ -641,6 +641,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
uint64_t q; uint64_t q;
asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
return q; return q;
#elif defined(__s390x__)
/* Need to use a TImode type to get an even register pair for DLGR. */
unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
asm("dlgr %0, %1" : "+r"(n) : "r"(d));
*r = n >> 64;
return n;
#else #else
uint64_t d0, d1, q0, q1, r1, r0, m; uint64_t d0, d1, q0, q1, r1, r0, m;