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tcg/aarch64: limit mul_vec size

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In AdvSIMD we can only do 32x32 integer multiples although SVE is
capable of larger 64 bit multiples. As a result we can end up
generating invalid opcodes. Fix this by only reprting we can emit
mul vector ops if the size is small enough.

Fixes a crash on:

sve-all-short-v8.3+sve@vq3/insn_mul_z_zi___INC.risu.bin

When running on AArch64 hardware.

Backports commit e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf from qemu
This commit is contained in:
Alex Bennée 2018-07-21 14:15:47 -04:00 committed by Lioncash
parent 4e40d9d2df
commit 11948dd1cc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
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3
qemu/tcg/aarch64/tcg-target.inc.c
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@ -2219,7 +2219,6 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
switch (opc) { switch (opc) {
case INDEX_op_add_vec: case INDEX_op_add_vec:
case INDEX_op_sub_vec: case INDEX_op_sub_vec:
case INDEX_op_mul_vec:
case INDEX_op_and_vec: case INDEX_op_and_vec:
case INDEX_op_or_vec: case INDEX_op_or_vec:
case INDEX_op_xor_vec: case INDEX_op_xor_vec:
@ -2232,6 +2231,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shri_vec: case INDEX_op_shri_vec:
case INDEX_op_sari_vec: case INDEX_op_sari_vec:
return 1; return 1;
case INDEX_op_mul_vec:
return vece < MO_64;
default: default:
return 0; return 0;