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target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

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manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 05:17:50 -04:00 committed by Lioncash
parent cb7c94fbc4
commit 177726afb8
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 34 additions and 30 deletions
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3
qemu/target/riscv/insn32.decode
View file

@ -36,11 +36,12 @@
# Argument sets:
&b imm rs2 rs1
&i imm rs1 rd
&r rd rs1 rs2
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1

21
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -325,14 +325,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@ -355,8 +353,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@ -373,14 +370,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@ -430,14 +425,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
return true;
return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)

40
qemu/target/riscv/translate.c
View file

@ -212,12 +212,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(ctx, source2, rs2);
switch (opc) {
CASE_OP_32_64(OPC_RISC_ADD):
tcg_gen_add_tl(tcg_ctx, source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_SUB):
tcg_gen_sub_tl(tcg_ctx, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SLLW:
tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F);
@ -234,9 +228,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
case OPC_RISC_SLTU:
tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LTU, source1, source1, source2);
break;
case OPC_RISC_XOR:
tcg_gen_xor_tl(tcg_ctx, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_SRLW:
/* clear upper 32 */
@ -262,12 +253,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1);
tcg_gen_sar_tl(tcg_ctx, source1, source1, source2);
break;
case OPC_RISC_OR:
tcg_gen_or_tl(tcg_ctx, source1, source1, source2);
break;
case OPC_RISC_AND:
tcg_gen_and_tl(tcg_ctx, source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@ -754,8 +739,33 @@ static void gen_addw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_add_tl(tcg_ctx, ret, arg1, arg2);
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
}
static void gen_subw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_sub_tl(tcg_ctx, ret, arg1, arg2);
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
}
#endif
static bool trans_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, source1, a->rs1);
gen_get_gpr(ctx, source2, a->rs2);
(*func)(tcg_ctx, source1, source1, source2);
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"