From 2392d8b8ab2fd632a14ccf415745e60b0c2a4181 Mon Sep 17 00:00:00 2001 From: Amir Charif Date: Tue, 19 Mar 2019 05:42:50 -0400 Subject: [PATCH] target/arm: Check access permission to ADDVL/ADDPL/RDVL These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Backports commit 5de56742a3c91de3d646326bec43a989bba83ca4 from qemu --- qemu/target/arm/translate-sve.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 9c0a33a8..85c3a20b 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -999,27 +999,33 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv_i64 rd = cpu_reg_sp(s, a->rd); - TCGv_i64 rn = cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * vec_full_reg_size(s)); + } return true; } static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv_i64 rd = cpu_reg_sp(s, a->rd); - TCGv_i64 rn = cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * pred_full_reg_size(s)); + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * pred_full_reg_size(s)); + } return true; } static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv_i64 reg = cpu_reg(s, a->rd); - tcg_gen_movi_i64(tcg_ctx, reg, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i64 reg = cpu_reg(s, a->rd); + tcg_gen_movi_i64(tcg_ctx, reg, a->imm * vec_full_reg_size(s)); + } return true; }