diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 95476877..b98b0acd 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -4078,7 +4078,8 @@ mips_symbols = (
     'mips_reg_read',
     'mips_reg_write',
     'mips_tcg_init',
-    'mips_cpu_list'
+    'mips_cpu_list',
+    'mips_release'
 )
 
 sparc_symbols = (
diff --git a/qemu/hw/mips/mips_r4k.c b/qemu/hw/mips/mips_r4k.c
index 0482567c..6d48ac43 100644
--- a/qemu/hw/mips/mips_r4k.c
+++ b/qemu/hw/mips/mips_r4k.c
@@ -35,8 +35,8 @@ static int mips_r4k_init(struct uc_struct *uc, MachineState *machine)
 #endif
     }
 
-    cpu = cpu_mips_init(uc, cpu_model);
-    if (cpu == NULL) {
+    uc->cpu = (void*) cpu_mips_init(uc, cpu_model);
+    if (uc->cpu == NULL) {
         fprintf(stderr, "Unable to find CPU definition\n");
         return -1;
     }
diff --git a/qemu/mips.h b/qemu/mips.h
index 58113dce..f88ee66a 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -4070,4 +4070,5 @@
 #define mips_reg_write mips_reg_write_mips
 #define mips_tcg_init mips_tcg_init_mips
 #define mips_cpu_list mips_cpu_list_mips
+#define mips_release mips_release_mips
 #endif
diff --git a/qemu/mips64.h b/qemu/mips64.h
index d1a106f0..2422ea67 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -4070,4 +4070,5 @@
 #define mips_reg_write mips_reg_write_mips64
 #define mips_tcg_init mips_tcg_init_mips64
 #define mips_cpu_list mips_cpu_list_mips64
+#define mips_release mips_release_mips64
 #endif
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 95505a7b..9ca8d02b 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -4070,4 +4070,5 @@
 #define mips_reg_write mips_reg_write_mips64el
 #define mips_tcg_init mips_tcg_init_mips64el
 #define mips_cpu_list mips_cpu_list_mips64el
+#define mips_release mips_release_mips64el
 #endif
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index beabca5e..d097143b 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -4070,4 +4070,5 @@
 #define mips_reg_write mips_reg_write_mipsel
 #define mips_tcg_init mips_tcg_init_mipsel
 #define mips_cpu_list mips_cpu_list_mipsel
+#define mips_release mips_release_mipsel
 #endif
diff --git a/qemu/target-mips/unicorn.c b/qemu/target-mips/unicorn.c
index ec8779bf..94c1819f 100644
--- a/qemu/target-mips/unicorn.c
+++ b/qemu/target-mips/unicorn.c
@@ -30,6 +30,34 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address)
     ((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address;
 }
 
+
+void mips_release(void *ctx);
+void mips_release(void *ctx)
+{
+    int i;
+    TCGContext *tcg_ctx = (TCGContext *) ctx;
+    release_common(ctx);
+    MIPSCPU* cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
+    g_free(cpu->env.tlb);
+    g_free(cpu->env.mvp);
+
+    for (i = 0; i < MIPS_DSP_ACC; i++) {
+        g_free(tcg_ctx->cpu_HI[i]);
+        g_free(tcg_ctx->cpu_LO[i]);
+    }
+
+    for (i = 0; i < 32; i++) {
+        g_free(tcg_ctx->cpu_gpr[i]);
+    }
+
+    g_free(tcg_ctx->cpu_PC);
+    g_free(tcg_ctx->btarget);
+    g_free(tcg_ctx->bcond);
+    g_free(tcg_ctx->cpu_dspctrl);
+
+    g_free(tcg_ctx->tb_ctx.tbs);
+}
+
 void mips_reg_reset(struct uc_struct *uc)
 {
     (void)uc;
@@ -109,6 +137,7 @@ __attribute__ ((visibility ("default")))
     uc->reg_read = mips_reg_read;
     uc->reg_write = mips_reg_write;
     uc->reg_reset = mips_reg_reset;
+    uc->release = mips_release;
     uc->set_pc = mips_set_pc;
     uc->mem_redirect = mips_mem_redirect;
     uc_common_init(uc);