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tcg: Pass generic CPUState to gen_intermediate_code()

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Needed to implement a target-agnostic gen_intermediate_code()
in the future.

Backports commit 9c489ea6bed134fecfd556b439c68bba48fbe102 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-03 23:25:31 -05:00 committed by Lioncash
parent 382dcb2deb
commit 32b3c3815d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
9 changed files with 18 additions and 22 deletions
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2
qemu/include/exec/exec-all.h
View file

@ -66,7 +66,7 @@ typedef ram_addr_t tb_page_addr_t;
#include "qemu/log.h"
void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
target_ulong *data);
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);

6
qemu/target/arm/translate-a64.c
View file

@ -11416,10 +11416,10 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;

6
qemu/target/arm/translate.c
View file

@ -11991,10 +11991,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
@ -12010,7 +12010,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
gen_intermediate_code_a64(cpu, tb);
gen_intermediate_code_a64(cs, tb);
return;
}

4
qemu/target/arm/translate.h
View file

@ -148,14 +148,14 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
#ifdef TARGET_AARCH64
void a64_translate_init(struct uc_struct *uc);
void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
#else
static inline void a64_translate_init(struct uc_struct *uc)
{
}
static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
{
}

5
qemu/target/i386/translate.c
View file

@ -9144,10 +9144,9 @@ void tcg_x86_init(struct uc_struct *uc)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUX86State *env = cs->env_ptr;
TCGContext *tcg_ctx = env->uc->tcg_ctx;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;

5
qemu/target/m68k/translate.c
View file

@ -5732,10 +5732,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
M68kCPU *cpu = m68k_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUM68KState *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
int pc_offset;

5
qemu/target/mips/translate.c
View file

@ -20013,10 +20013,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
}
}
void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUMIPSState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;

5
qemu/target/sparc/translate.c
View file

@ -5921,10 +5921,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
}
}
void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
{
SPARCCPU *cpu = sparc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUSPARCState *env = cs->env_ptr;
target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
int num_insns = 0;

2
qemu/translate-all.c
View file

@ -1334,7 +1334,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(tcg_ctx);
tcg_ctx->cpu = ENV_GET_CPU(env);
gen_intermediate_code(env, tb);
gen_intermediate_code(cpu, tb);
tcg_ctx->cpu = NULL;
// Unicorn: when tracing block, patch block size operand for callback