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tcg/i386: fix vector operations on 32-bit hosts

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The TCG backend uses LOWREGMASK to get the low 3 bits of register numbers.
This was defined as no-op for 32-bit x86, with the assumption that we have
eight registers anyway. This assumption is not true once we have xmm regs.

Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes
and have overflown into other opcode fields, wreaking havoc.

To trigger these problems, you can try running the "movi d8, #0x0" AArch64
instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated,
but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2".

Fixes: 770c2fc7bb ("Add vector operations")

Backports commit 93bf9a42733321fb632bcb9eafd049ef0e3d9417 from qemu
This commit is contained in:
Roman Kapl 2018-10-02 04:22:20 -04:00 committed by Lioncash
parent 04fead0dcb
commit 33e69342e3
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4
qemu/tcg/i386/tcg-target.inc.c
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@ -309,11 +309,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
return 0;
}
#if TCG_TARGET_REG_BITS == 64
# define LOWREGMASK(x) ((x) & 7)
#else
# define LOWREGMASK(x) (x)
#endif
#define P_EXT 0x100 /* 0x0f opcode prefix */
#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */