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tcg/aarch64: Fix tcg_out_qemu_{ld, st} for guest_base == 0
In ffc6372851d8631a9f9fa56ec613b3244dc635b9, we swapped the guest base to the address base register from the address index register. Except that 31 in the base slot is SP not XZR, so we need to be more intelligent about which reg gets placed in which slot. Backports commit 352bcb0a2b816ff9ab9d75d0f2384650d9e9ab19 from qemu
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parent
7d57c2e4ce
commit
352f93a119
1 changed files with 19 additions and 6 deletions
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@ -56,6 +56,11 @@ static const int tcg_target_call_oarg_regs[1] = {
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#define TCG_REG_TMP TCG_REG_X30
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#ifndef CONFIG_SOFTMMU
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/* Note that XZR cannot be encoded in the address base register slot,
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as that actaully encodes SP. So if we need to zero-extend the guest
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address, via the address index register slot, we need to load even
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a zero guest base into a register. */
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#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32)
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# ifdef CONFIG_USE_GUEST_BASE
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# define TCG_REG_GUEST_BASE TCG_REG_X28
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# else
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@ -1228,9 +1233,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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if (USE_GUEST_BASE) {
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tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR,
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otype, addr_reg);
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TCG_REG_GUEST_BASE, otype, addr_reg);
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} else {
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tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
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}
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#endif /* CONFIG_SOFTMMU */
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}
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@ -1249,9 +1258,13 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
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data_reg, addr_reg, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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if (USE_GUEST_BASE) {
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tcg_out_qemu_st_direct(s, memop, data_reg,
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GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR,
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otype, addr_reg);
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TCG_REG_GUEST_BASE, otype, addr_reg);
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} else {
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tcg_out_qemu_st_direct(s, memop, data_reg,
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addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
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}
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#endif /* CONFIG_SOFTMMU */
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}
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