From 3e9325f1e99fc737093a178ea88b9fd21ebb1325 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Sat, 24 Feb 2018 20:40:07 -0500 Subject: [PATCH] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd() Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct the order of argument comparisons in pickNaNMulAdd(). For more info, see [1], page 53, section "3.5.3 NaN Propagation". [1] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Backports commit c27644f0e9659471e1c9355da5b667960d311937 from qemu --- qemu/fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/qemu/fpu/softfloat-specialize.h b/qemu/fpu/softfloat-specialize.h index 3e3a4d98..570af1e2 100644 --- a/qemu/fpu/softfloat-specialize.h +++ b/qemu/fpu/softfloat-specialize.h @@ -569,19 +569,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 3; } - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (cIsSNaN) { - return 2; - } else if (aIsQNaN) { - return 0; - } else if (bIsQNaN) { - return 1; + if (status->snan_bit_is_one) { + /* Prefer sNaN over qNaN, in the a, b, c order. */ + if (aIsSNaN) { + return 0; + } else if (bIsSNaN) { + return 1; + } else if (cIsSNaN) { + return 2; + } else if (aIsQNaN) { + return 0; + } else if (bIsQNaN) { + return 1; + } else { + return 2; + } } else { - return 2; + /* Prefer sNaN over qNaN, in the c, a, b order. */ + if (cIsSNaN) { + return 2; + } else if (aIsSNaN) { + return 0; + } else if (bIsSNaN) { + return 1; + } else if (cIsQNaN) { + return 2; + } else if (aIsQNaN) { + return 0; + } else { + return 1; + } } } #elif defined(TARGET_PPC)