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unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers

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Avoids directly touching the representation of the VFP/NEON/SIMD registers
This commit is contained in:
Lioncash 2018-03-07 11:07:31 -05:00
parent 9e14a824ed
commit 5439b4a542
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 35 additions and 23 deletions
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40
qemu/target/arm/unicorn_aarch64.c
View file

@ -63,17 +63,22 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
*(int32_t *)value = READ_DWORD(state->xregs[regid - UC_ARM64_REG_W0]);
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *dst = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
dst[0] = state->vfp.regs[reg_index];
dst[1] = state->vfp.regs[reg_index+1];
const uint32_t reg_index = regid - UC_ARM64_REG_Q0;
const float64 *q_reg = aa64_vfp_qreg(state, reg_index);
dst[0] = q_reg[0];
dst[1] = q_reg[1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
*(float64*)value = state->vfp.regs[2*(regid - UC_ARM64_REG_D0)];
const float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_D0));
*(float64*)value = *d_reg;
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
*(int32_t*)value = READ_DWORD(state->vfp.regs[2*(regid - UC_ARM64_REG_S0)]);
const float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_S0));
*(int32_t*)value = READ_DWORD(*d_reg);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
*(int16_t*)value = READ_WORD(state->vfp.regs[2*(regid - UC_ARM64_REG_H0)]);
const float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_H0));
*(int16_t*)value = READ_WORD(*d_reg);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
*(int8_t*)value = READ_BYTE_L(state->vfp.regs[2*(regid - UC_ARM64_REG_B0)]);
const float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_B0));
*(int8_t*)value = READ_BYTE_L(*d_reg);
} else {
switch(regid) {
default: break;
@ -140,18 +145,23 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
WRITE_DWORD(state->xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
float64 *src = (float64*) value;
uint32_t reg_index = 2*(regid - UC_ARM64_REG_Q0);
state->vfp.regs[reg_index] = src[0];
state->vfp.regs[reg_index+1] = src[1];
const float64 *src = (const float64*) value;
const uint32_t reg_index = regid - UC_ARM64_REG_Q0;
float64 *q_reg = aa64_vfp_qreg(state, reg_index);
q_reg[0] = src[0];
q_reg[1] = src[1];
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
state->vfp.regs[2*(regid - UC_ARM64_REG_D0)] = * (float64*) value;
float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_D0));
*d_reg = *(float64*) value;
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
WRITE_DWORD(state->vfp.regs[2*(regid - UC_ARM64_REG_S0)], *(int32_t*) value);
float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_S0));
WRITE_DWORD(*d_reg, *(int32_t*) value);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
WRITE_WORD(state->vfp.regs[2*(regid - UC_ARM64_REG_H0)], *(int16_t*) value);
float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_H0));
WRITE_WORD(*d_reg, *(int16_t*) value);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
WRITE_BYTE_L(state->vfp.regs[2*(regid - UC_ARM64_REG_B0)], *(int8_t*) value);
float64 *d_reg = aa32_vfp_dreg(state, 2 * (regid - UC_ARM64_REG_B0));
WRITE_BYTE_L(*d_reg, *(int8_t*) value);
} else {
switch(regid) {
default: break;

18
qemu/target/arm/unicorn_arm.c
View file

@ -59,11 +59,12 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
*(int32_t *)value = state->regs[regid - UC_ARM_REG_R0];
else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31)
*(float64 *)value = state->vfp.regs[regid - UC_ARM_REG_D0];
else {
} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
const float64 *d_reg = aa32_vfp_dreg(state, regid - UC_ARM64_REG_D0);
*(float64 *)value = *d_reg;
} else {
switch(regid) {
case UC_ARM_REG_APSR:
*(int32_t *)value = cpsr_read(state) & CPSR_NZCV;
@ -108,11 +109,12 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
state->regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31)
state->vfp.regs[regid - UC_ARM_REG_D0] = *(float64 *)value;
else {
} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
float64 *d_reg = aa32_vfp_dreg(state, regid - UC_ARM64_REG_D0);
*d_reg = *(float64 *)value;
} else {
switch(regid) {
case UC_ARM_REG_APSR:
cpsr_write(state, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw);