From 5fabebabeea3aa7a7240ad4d2a2a6dd3067e1ce0 Mon Sep 17 00:00:00 2001 From: Michael Weiser Date: Tue, 6 Mar 2018 08:45:34 -0500 Subject: [PATCH] target/arm: Fix stlxp for aarch64_be ldxp loads two consecutive doublewords from memory regardless of CPU endianness. On store, stlxp currently assumes to work with a 128bit value and consequently switches order in big-endian mode. With this change it packs the doublewords in reverse order in anticipation of the 128bit big-endian store operation interposing them so they end up in memory in the right order. This makes it work for both MTTCG and !MTTCG. It effectively implements the ARM ARM STLXP operation pseudo-code: data = if BigEndian() then el1:el2 else el2:el1; With this change an aarch64_be Linux 4.14.4 kernel succeeds to boot up in system emulation mode. Backports commit 0785557f8811133bd69be02aeccf018d47a26373 from qemu --- qemu/target/arm/helper-a64.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 0d0f0416..f5ae40e9 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -506,8 +506,11 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, Int128 oldv, cmpv, newv; bool success; - cmpv = int128_make128(env->exclusive_val, env->exclusive_high); - newv = int128_make128(new_lo, new_hi); + /* high and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + cmpv = int128_make128(env->exclusive_high, env->exclusive_val); + newv = int128_make128(new_hi, new_lo); if (env->uc->parallel_cpus) { #ifndef CONFIG_ATOMIC128