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tcg/sparc: Add support for fence

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Backports commit f8f03b3707b49898052fb8cd75ee31d19c8161fc from qemu
This commit is contained in:
Pranith Kumar 2018-02-26 03:20:35 -05:00 committed by Lioncash
parent a6fdc24e28
commit 65a73763e3
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 13 additions and 0 deletions
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13
qemu/tcg/sparc/tcg-target.inc.c
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@ -251,6 +251,8 @@ static const int tcg_target_call_oarg_regs[] = {
#define STWA (INSN_OP(3) | INSN_OP3(0x14))
#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
#ifndef ASI_PRIMARY_LITTLE
#define ASI_PRIMARY_LITTLE 0x88
#endif
@ -837,6 +839,12 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
tcg_out_nop(s);
}
static void tcg_out_mb(TCGContext *s, TCGArg a0)
{
/* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
}
#ifdef CONFIG_SOFTMMU
static tcg_insn_unit *qemu_ld_trampoline[16];
static tcg_insn_unit *qemu_st_trampoline[16];
@ -1468,6 +1476,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@ -1569,6 +1581,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_st_i32, { "sZ", "A" } },
{ INDEX_op_qemu_st_i64, { "SZ", "A" } },
{ INDEX_op_mb, { } },
{ -1 },
};