hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC

Instead of hardcoding the values of M profile ID registers in the
NVIC, use the fields in the CPU struct. This will allow us to
give different M profile CPU types different ID register values.

This commit includes the addition of the missing ID_ISAR5,
which exists as RES0 in both v7M and v8M.

(The values of the ID registers might be wrong for the M4 --
this commit leaves the behaviour there unchanged.)

Backports commit 5a53e2c1dc939fea1af92cc126ee546d8211d412 from qemu
This commit is contained in:
Peter Maydell 2018-03-08 09:33:46 -05:00 committed by Lioncash
parent 1f71084740
commit 6f31c219b9
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GPG key ID: 4E3C3CC1031BA9C7

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@ -939,6 +939,20 @@ static void cortex_m3_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = 0x410fc231;
cpu->pmsav7_dregion = 8;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
cpu->id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x00000000;
cpu->id_mmfr3 = 0x00000000;
cpu->id_isar0 = 0x01141110;
cpu->id_isar1 = 0x02111000;
cpu->id_isar2 = 0x21112231;
cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000;
}
static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@ -950,6 +964,20 @@ static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
cpu->midr = 0x410fc240; /* r0p0 */
cpu->pmsav7_dregion = 8;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
cpu->id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x00000000;
cpu->id_mmfr3 = 0x00000000;
cpu->id_isar0 = 0x01141110;
cpu->id_isar1 = 0x02111000;
cpu->id_isar2 = 0x21112231;
cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000;
}
static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)