From 6fac3fee4ecbc03e7a7cc1052c0df9a1865b33e4 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 14 Feb 2018 16:59:06 -0500 Subject: [PATCH] target-mips: fix to clear MSACSR.Cause MSACSR.Cause bits are needed to be cleared before a vector floating-point instructions. FEXDO.df, FEXUPL.df and FEXUPR.df were missed out. Backports commit d4f4f0d5d9e74c19614479592c8bc865d92773d0 from qemu --- qemu/target-mips/msa_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/target-mips/msa_helper.c b/qemu/target-mips/msa_helper.c index 1af89082..c00fa178 100644 --- a/qemu/target-mips/msa_helper.c +++ b/qemu/target-mips/msa_helper.c @@ -2639,6 +2639,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwt = &(env->active_fpu.fpr[wt].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3189,6 +3191,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3221,6 +3225,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {