From 72677eadd0e0b14a756898086f8b568b887327ad Mon Sep 17 00:00:00 2001 From: James Hogan Date: Sat, 3 Mar 2018 23:40:35 -0500 Subject: [PATCH] target/mips: Weaken TLB flush on UX,SX,KX,ASID changes There is no need to invalidate any shadow TLB entries when the ASID changes or when access to one of the 64-bit segments has been disabled, since doing so doesn't reveal to software whether any TLB entries have been evicted into the shadow half of the TLB. Therefore weaken the tlb flushes in these cases to only flush the QEMU TLB. Backports commit 9658e4c342e6ae0d775101f8f6bb6efb16789af1 from qemu --- qemu/target/mips/helper.c | 2 +- qemu/target/mips/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/mips/helper.c b/qemu/target/mips/helper.c index f4679c2c..f4e422b0 100644 --- a/qemu/target/mips/helper.c +++ b/qemu/target/mips/helper.c @@ -278,7 +278,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled */ - cpu_mips_tlb_flush(env); + tlb_flush(CPU(mips_env_get_cpu(env))); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c index a1097b1d..48c83464 100644 --- a/qemu/target/mips/op_helper.c +++ b/qemu/target/mips/op_helper.c @@ -1410,7 +1410,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) != (val & env->CP0_EntryHi_ASID_mask)) { - cpu_mips_tlb_flush(env); + tlb_flush(CPU(mips_env_get_cpu(env))); } }