From 7473e6dbe62dbedf11d578d0528d2d8652a756ac Mon Sep 17 00:00:00 2001
From: Stefan Markovic <smarkovic@wavecomp.com>
Date: Mon, 27 Aug 2018 14:59:58 -0400
Subject: [PATCH] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS

Update BadInstr and BadInstrX registers for nanoMIPS. The same
support for pre-nanoMIPS remains unimplemented.

Backports commit 7a5f784aa215df6bf5d674b4003f8df43bf3b2d4 from qemu
---
 qemu/target/mips/helper.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/qemu/target/mips/helper.c b/qemu/target/mips/helper.c
index 5c83017b..3acfd90c 100644
--- a/qemu/target/mips/helper.c
+++ b/qemu/target/mips/helper.c
@@ -671,6 +671,22 @@ static void set_hflags_for_handler (CPUMIPSState *env)
 
 static inline void set_badinstr_registers(CPUMIPSState *env)
 {
+    if (env->insn_flags & ISA_NANOMIPS32) {
+        if (env->CP0_Config3 & (1 << CP0C3_BI)) {
+            uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
+            if ((instr & 0x10000000) == 0) {
+                instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
+            }
+            env->CP0_BadInstr = instr;
+
+            if ((instr & 0xFC000000) == 0x60000000) {
+                instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+                env->CP0_BadInstrX = instr;
+            }
+        }
+        return;
+    }
+
     if (env->hflags & MIPS_HFLAG_M16) {
         /* TODO: add BadInstr support for microMIPS */
         return;