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target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2

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The AArch32 HSR is the equivalent of AArch64 ESR_EL2;
we can implement it by marking our existing ESR_EL2 regdef
as STATE_BOTH. It also needs to be "RES0 from EL3 if
EL2 not implemented", so add the missing stanza to
el3_no_el2_cp_reginfo.

Backports commit 68e78e332cb1c3f8b0317a0443acb2b5e190f0dd from qemu
This commit is contained in:
Peter Maydell 2018-08-22 12:48:32 -04:00 committed by Lioncash
parent c21d2062e4
commit 858aa2d094
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
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4
qemu/target/arm/helper.c
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@ -3352,6 +3352,8 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64, { "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL2_RW, 0, NULL, 0, 0, {0, 0}, ARM_CP_NO_RAW, PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, arm_cp_read_zero, arm_cp_write_ignore }, NULL, arm_cp_read_zero, arm_cp_write_ignore },
{ "ESR_EL2", 0,5,2, 3,1,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST, { "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 }, PL2_RW, 0, NULL, 0 },
{ "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, { "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
@ -3451,7 +3453,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
NULL, NULL, hcr_write }, NULL, NULL, hcr_write },
{ "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64, { "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) }, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0, { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) }, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH, { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) }, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },