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target/arm: Decode t32 simd 3reg and 2reg_scalar extension

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Happily, the bits are in the same places compared to a32.

Backports commit 0052087efb8a5c0e29ddc2f59f8476fcdc6495b2 from qemu
This commit is contained in:
Richard Henderson 2018-03-09 01:11:12 -05:00 committed by Lioncash
parent e5da25aaf8
commit 85cfb78ea2
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 13 additions and 1 deletions
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14
qemu/target/arm/translate.c
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@ -10956,7 +10956,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
default_exception_el(s));
break;
}
if (((insn >> 24) & 3) == 3) {
if ((insn & 0xfe000a00) == 0xfc000800
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
/* The Thumb2 and ARM encodings are identical. */
if (disas_neon_insn_3same_ext(s, insn)) {
goto illegal_op;
}
} else if ((insn & 0xff000a00) == 0xfe000800
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
/* The Thumb2 and ARM encodings are identical. */
if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
goto illegal_op;
}
} else if (((insn >> 24) & 3) == 3) {
/* Translate into the equivalent ARM encoding. */
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
if (disas_neon_data_insn(s, insn)) {