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https://github.com/yuzu-emu/unicorn
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target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Backports commit 5204ea79ea739b557f47fc4db96c94edcb33a5d6 from qemu
This commit is contained in:
Leon Alrae
Lioncash
parent
59865351e0
commit
8743ec8b6d
2 changed files with 224 additions and 0 deletions
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@ -474,6 +474,7 @@ struct CPUMIPSState {
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#define CP0C5_UFE 9
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#define CP0C5_FRE 8
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#define CP0C5_SBRI 6
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#define CP0C5_MVH 5
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#define CP0C5_LLB 4
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#define CP0C5_UFR 2
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#define CP0C5_NFExists 0
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@ -865,8 +865,10 @@ enum {
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enum {
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OPC_MFC0 = (0x00 << 21) | OPC_CP0,
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OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
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OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
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OPC_MTC0 = (0x04 << 21) | OPC_CP0,
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OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
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OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
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OPC_MFTR = (0x08 << 21) | OPC_CP0,
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OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
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OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
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@ -1407,6 +1409,9 @@ typedef struct DisasContext {
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int ie;
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bool bi;
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bool bp;
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uint64_t PAMask;
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bool mvh;
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int CP0_LLAddr_shift;
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// Unicorn engine
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struct uc_struct *uc;
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} DisasContext;
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@ -1823,6 +1828,15 @@ static inline void check_mips_64(DisasContext *ctx)
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline void check_mvh(DisasContext *ctx)
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{
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if (unlikely(!ctx->mvh)) {
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generate_exception(ctx, EXCP_RI);
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}
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}
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#endif
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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all callers for gen_load_fpr32 when we need the CTX parameter for
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@ -4901,6 +4915,60 @@ static inline void gen_move_low32(TCGContext *s, TCGv ret, TCGv_i64 arg)
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#endif
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}
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static inline void gen_mthc0_entrylo(TCGContext *s, TCGv arg, target_ulong off)
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{
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TCGv_i64 t0 = tcg_temp_new_i64(s);
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TCGv_i64 t1 = tcg_temp_new_i64(s);
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tcg_gen_ext_tl_i64(s, t0, arg);
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tcg_gen_ld_i64(s, t1, s->cpu_env, off);
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#if defined(TARGET_MIPS64)
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tcg_gen_deposit_i64(s, t1, t1, t0, 30, 32);
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#else
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tcg_gen_concat32_i64(s, t1, t1, t0);
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#endif
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tcg_gen_st_i64(s, t1, s->cpu_env, off);
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tcg_temp_free_i64(s, t1);
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tcg_temp_free_i64(s, t0);
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}
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static inline void gen_mthc0_store64(TCGContext *s, TCGv arg, target_ulong off)
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{
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TCGv_i64 t0 = tcg_temp_new_i64(s);
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TCGv_i64 t1 = tcg_temp_new_i64(s);
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tcg_gen_ext_tl_i64(s, t0, arg);
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tcg_gen_ld_i64(s, t1, s->cpu_env, off);
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tcg_gen_concat32_i64(s, t1, t1, t0);
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tcg_gen_st_i64(s, t1, s->cpu_env, off);
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tcg_temp_free_i64(s, t1);
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tcg_temp_free_i64(s, t0);
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}
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static inline void gen_mfhc0_entrylo(TCGContext *s, TCGv arg, target_ulong off)
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{
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TCGv_i64 t0 = tcg_temp_new_i64(s);
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tcg_gen_ld_i64(s, t0, s->cpu_env, off);
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#if defined(TARGET_MIPS64)
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tcg_gen_shri_i64(s, t0, t0, 30);
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#else
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tcg_gen_shri_i64(s, t0, t0, 32);
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#endif
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gen_move_low32(s, arg, t0);
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tcg_temp_free_i64(s, t0);
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}
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static inline void gen_mfhc0_load64(TCGContext *s, TCGv arg, target_ulong off, int shift)
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{
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TCGv_i64 t0 = tcg_temp_new_i64(s);
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tcg_gen_ld_i64(s, t0, s->cpu_env, off);
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tcg_gen_shri_i64(s, t0, t0, 32 + shift);
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gen_move_low32(s, arg, t0);
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tcg_temp_free_i64(s, t0);
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}
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static inline void gen_mfc0_load32 (DisasContext *ctx, TCGv arg, target_ulong off)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -4935,6 +5003,142 @@ static inline void gen_mtc0_store64 (DisasContext *ctx, TCGv arg, target_ulong o
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tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, off);
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}
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static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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TCGContext *s = ctx->uc->tcg_ctx;
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const char *rn = "invalid";
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if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
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goto mfhc0_read_zero;
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}
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switch (reg) {
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case 2:
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switch (sel) {
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case 0:
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gen_mfhc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
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rn = "EntryLo0";
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break;
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default:
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goto mfhc0_read_zero;
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}
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break;
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case 3:
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switch (sel) {
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case 0:
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gen_mfhc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo1));
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rn = "EntryLo1";
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break;
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default:
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goto mfhc0_read_zero;
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}
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break;
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case 17:
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switch (sel) {
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case 0:
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gen_mfhc0_load64(s, arg, offsetof(CPUMIPSState, lladdr),
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ctx->CP0_LLAddr_shift);
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rn = "LLAddr";
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break;
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default:
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goto mfhc0_read_zero;
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}
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break;
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case 28:
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switch (sel) {
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case 0:
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case 2:
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case 4:
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case 6:
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gen_mfhc0_load64(s, arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
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rn = "TagLo";
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break;
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default:
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goto mfhc0_read_zero;
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}
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break;
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default:
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goto mfhc0_read_zero;
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}
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(void)rn; /* avoid a compiler warning */
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LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
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return;
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mfhc0_read_zero:
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LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
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tcg_gen_movi_tl(s, arg, 0);
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}
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static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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TCGContext *s = ctx->uc->tcg_ctx;
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const char *rn = "invalid";
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uint64_t mask = ctx->PAMask >> 36;
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if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
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goto mthc0_nop;
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}
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switch (reg) {
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case 2:
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switch (sel) {
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case 0:
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tcg_gen_andi_tl(s, arg, arg, mask);
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gen_mthc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
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rn = "EntryLo0";
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break;
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default:
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goto mthc0_nop;
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}
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break;
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case 3:
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switch (sel) {
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case 0:
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tcg_gen_andi_tl(s, arg, arg, mask);
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gen_mthc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo1));
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rn = "EntryLo1";
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break;
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default:
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goto mthc0_nop;
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}
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break;
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case 17:
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switch (sel) {
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case 0:
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/* LLAddr is read-only (the only exception is bit 0 if LLB is
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supported); the CP0_LLAddr_rw_bitmask does not seem to be
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relevant for modern MIPS cores supporting MTHC0, therefore
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treating MTHC0 to LLAddr as NOP. */
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rn = "LLAddr";
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break;
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default:
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goto mthc0_nop;
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}
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break;
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case 28:
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switch (sel) {
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case 0:
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case 2:
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case 4:
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case 6:
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tcg_gen_andi_tl(s, arg, arg, mask);
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gen_mthc0_store64(s, arg, offsetof(CPUMIPSState, CP0_TagLo));
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rn = "TagLo";
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break;
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default:
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goto mthc0_nop;
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}
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break;
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default:
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goto mthc0_nop;
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}
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(void)rn; /* avoid a compiler warning */
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mthc0_nop:
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LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
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}
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static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -7949,6 +8153,25 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
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opn = "dmtc0";
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break;
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#endif
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case OPC_MFHC0:
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check_mvh(ctx);
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if (rt == 0) {
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/* Treat as NOP. */
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return;
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}
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gen_mfhc0(ctx, *cpu_gpr[rt], rd, ctx->opcode & 0x7);
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opn = "mfhc0";
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break;
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case OPC_MTHC0:
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check_mvh(ctx);
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{
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TCGv t0 = tcg_temp_new(tcg_ctx);
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gen_load_gpr(ctx, t0, rt);
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gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
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tcg_temp_free(tcg_ctx, t0);
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}
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opn = "mthc0";
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break;
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case OPC_MFTR:
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check_insn(ctx, ASE_MT);
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if (rd == 0) {
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