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softfloat: Specialize udiv_qrnnd for x86_64

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The ISA has a 128/64-bit division instruction.

Backports commit b299e88d4261b0af30190e74005ad930e04f3a11 from qemu
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Richard Henderson 2018-10-08 11:06:52 -04:00 committed by Lioncash
parent 90fdf9b598
commit 8de4da1475
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/fpu/softfloat-macros.h
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@ -637,6 +637,11 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
uint64_t n0, uint64_t d) uint64_t n0, uint64_t d)
{ {
#if defined(__x86_64__)
uint64_t q;
asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
return q;
#else
uint64_t d0, d1, q0, q1, r1, r0, m; uint64_t d0, d1, q0, q1, r1, r0, m;
d0 = (uint32_t)d; d0 = (uint32_t)d;
@ -676,6 +681,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
*r = r0; *r = r0;
return (q1 << 32) | q0; return (q1 << 32) | q0;
#endif
} }
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------