From a734ef815614c444ddddf2dbbaa58168e3fbe83f Mon Sep 17 00:00:00 2001
From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 17 Feb 2018 21:03:12 -0500
Subject: [PATCH] target-sparc: Split cpu_put_psr into side-effect and
 no-side-effect parts

For inbound migration we really want to be able to set the PSR without
having any side effects, but cpu_put_psr() calls cpu_check_irqs() which
might try to deliver CPU interrupts. Split cpu_put_psr() into the
no-side-effect and side-effect parts.

This includes reordering the cpu_check_irqs() to the end of cpu_put_psr(),
because that function may actually end up calling cpu_interrupt(), which
does not seem like a good thing to happen in the middle of updating the PSR.

Backports commit 4552a09dd4055c806b7df8c595dc0fb8951834be from qemu
---
 qemu/header_gen.py             |  1 +
 qemu/sparc.h                   |  1 +
 qemu/sparc64.h                 |  1 +
 qemu/target-sparc/cpu.h        |  1 +
 qemu/target-sparc/win_helper.c | 21 ++++++++++++++-------
 5 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 8daf6421..6ceffe67 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -4179,6 +4179,7 @@ sparc_symbols = (
     'cpu_set_cwp',
     'cpu_get_psr',
     'cpu_put_psr',
+    'cpu_put_psr_raw',
     'cpu_cwp_inc',
     'cpu_cwp_dec',
     'helper_save',
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 34f3fb34..b7e884a0 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -3210,6 +3210,7 @@
 #define cpu_set_cwp cpu_set_cwp_sparc
 #define cpu_get_psr cpu_get_psr_sparc
 #define cpu_put_psr cpu_put_psr_sparc
+#define cpu_put_psr_raw cpu_put_psr_raw_sparc
 #define cpu_cwp_inc cpu_cwp_inc_sparc
 #define cpu_cwp_dec cpu_cwp_dec_sparc
 #define helper_save helper_save_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index 32235ebf..c280330b 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -3210,6 +3210,7 @@
 #define cpu_set_cwp cpu_set_cwp_sparc64
 #define cpu_get_psr cpu_get_psr_sparc64
 #define cpu_put_psr cpu_put_psr_sparc64
+#define cpu_put_psr_raw cpu_put_psr_raw_sparc64
 #define cpu_cwp_inc cpu_cwp_inc_sparc64
 #define cpu_cwp_dec cpu_cwp_dec_sparc64
 #define helper_save helper_save_sparc64
diff --git a/qemu/target-sparc/cpu.h b/qemu/target-sparc/cpu.h
index 20f21eb0..3f30429a 100644
--- a/qemu/target-sparc/cpu.h
+++ b/qemu/target-sparc/cpu.h
@@ -542,6 +542,7 @@ int cpu_sparc_exec(struct uc_struct *uc, CPUState *cpu);
 /* win_helper.c */
 target_ulong cpu_get_psr(CPUSPARCState *env1);
 void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
+void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
 #ifdef TARGET_SPARC64
 target_ulong cpu_get_ccr(CPUSPARCState *env1);
 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
diff --git a/qemu/target-sparc/win_helper.c b/qemu/target-sparc/win_helper.c
index f077273c..ccdd909e 100644
--- a/qemu/target-sparc/win_helper.c
+++ b/qemu/target-sparc/win_helper.c
@@ -63,23 +63,30 @@ target_ulong cpu_get_psr(CPUSPARCState *env)
 #endif
 }
 
-void cpu_put_psr(CPUSPARCState *env, target_ulong val)
+void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
 {
     env->psr = val & PSR_ICC;
 #if !defined(TARGET_SPARC64)
     env->psref = (val & PSR_EF) ? 1 : 0;
     env->psrpil = (val & PSR_PIL) >> 8;
-#endif
-#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
-    //cpu_check_irqs(env);
-#endif
-#if !defined(TARGET_SPARC64)
+
     env->psrs = (val & PSR_S) ? 1 : 0;
     env->psrps = (val & PSR_PS) ? 1 : 0;
     env->psret = (val & PSR_ET) ? 1 : 0;
-    cpu_set_cwp(env, val & PSR_CWP);
 #endif
     env->cc_op = CC_OP_FLAGS;
+#if !defined(TARGET_SPARC64)
+    cpu_set_cwp(env, val & PSR_CWP);
+#endif
+}
+
+void cpu_put_psr(CPUSPARCState *env, target_ulong val)
+{
+    cpu_put_psr_raw(env, val);
+#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
+    // Unicorn: commented out
+    //cpu_check_irqs(env);
+#endif
 }
 
 int cpu_cwp_inc(CPUSPARCState *env, int cwp)