From afecfee565db653588a5627e83710f8a20531b72 Mon Sep 17 00:00:00 2001 From: mothran Date: Thu, 10 Sep 2015 23:20:52 -0700 Subject: [PATCH] added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64 --- qemu/target-sparc/unicorn.c | 23 +++++++++++++++++------ qemu/target-sparc/unicorn64.c | 26 +++++++++++++++++++------- 2 files changed, 36 insertions(+), 13 deletions(-) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 9f00f340..19e3ab0e 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -54,8 +54,14 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) switch(regid) { default: break; case UC_SPARC_REG_PC: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; - break; + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; + break; + case UC_SPARC_REG_SP: + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + break; + case UC_SPARC_REG_FP: + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + break; } } @@ -78,13 +84,18 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) switch(regid) { default: break; case UC_SPARC_REG_PC: - SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; - SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; - break; + SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; + break; + case UC_SPARC_REG_SP: + SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint32_t *)value; + break; + case UC_SPARC_REG_FP: + SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint32_t *)value; + break; } } - return 0; } diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index aefef116..eb88c095 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -32,13 +32,19 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) CPUState *mycpu = first_cpu; if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; else { switch(regid) { default: break; case UC_SPARC_REG_PC: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; - break; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.pc; + break; + case UC_SPARC_REG_SP: + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + break; + case UC_SPARC_REG_FP: + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + break; } } @@ -56,14 +62,20 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) CPUState *mycpu = first_cpu; if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) - SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint64_t *)value; else { switch(regid) { default: break; case UC_SPARC_REG_PC: - SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; - SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; - break; + SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; + SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8; + break; + case UC_SPARC_REG_SP: + SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint64_t *)value; + break; + case UC_SPARC_REG_FP: + SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint64_t *)value; + break; } }