From b247ee234d13fd3df1c5e8e20daa1325a084351e Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Tue, 19 Mar 2019 23:53:34 -0400 Subject: [PATCH] RISC-V: Update load reservation comment in do_interrupt Backports commit d9360e96885dbd69ce4aa925d1701c7a10cf54ae from qemu --- qemu/target/riscv/cpu_helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index b5b08558..a63f7eca 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -531,7 +531,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); } - /* TODO yield load reservation */ + + /* NOTE: it is not necessary to yield load reservations here. It is only + * necessary for an SC from "another hart" to cause a load reservation + * to be yielded. Refer to the memory consistency model section of the + * RISC-V ISA Specification. + */ + #endif cs->exception_index = EXCP_NONE; /* mark handled to qemu */ }