From c1dd9fbfdfdf5dedfecad82a61b73eca74adf9fd Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 8 Sep 2015 08:40:42 +0800 Subject: [PATCH] arm64: handle SP register. this fixes issue #122 --- qemu/target-arm/unicorn_aarch64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index cc6f4864..0123b5cb 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -51,6 +51,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int regid, void *value) case UC_ARM64_REG_PC: *(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc; break; + case UC_ARM64_REG_SP: + *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31]; + break; } } @@ -80,6 +83,9 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) case UC_ARM64_REG_PC: ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; break; + case UC_ARM64_REG_SP: + ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value; + break; } }