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arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Backports commit 7a2c6e618156674cf9eac8bf36e79f674fbf974e from qemu
This commit is contained in:
Alex Bennée
Lioncash
parent
4b2577537b
commit
c6fda07628
1 changed files with 132 additions and 75 deletions
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@ -10399,6 +10399,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
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int datasize, elements;
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int pass;
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TCGv_ptr fpst;
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bool pairwise = false;
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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@ -10424,91 +10425,147 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
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datasize = is_q ? 128 : 64;
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elements = datasize / 16;
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switch (fpopcode) {
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case 0x10: /* FMAXNMP */
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case 0x12: /* FADDP */
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case 0x16: /* FMAXP */
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case 0x18: /* FMINNMP */
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case 0x1e: /* FMINP */
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pairwise = true;
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break;
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}
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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for (pass = 0; pass < elements; pass++) {
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if (pairwise) {
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int maxpass = is_q ? 8 : 4;
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TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 tcg_res[8];
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read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
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for (pass = 0; pass < maxpass; pass++) {
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int passreg = pass < (maxpass / 2) ? rn : rm;
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int passelt = (pass << 1) & (maxpass - 1);
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switch (fpopcode) {
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case 0x0: /* FMAXNM */
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gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1: /* FMLA */
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read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
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fpst);
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break;
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case 0x2: /* FADD */
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gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3: /* FMULX */
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gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x4: /* FCMEQ */
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gen_helper_advsimd_ceq_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x6: /* FMAX */
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gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7: /* FRECPS */
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gen_helper_recpsf_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x8: /* FMINNM */
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gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x9: /* FMLS */
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/* As usual for ARM, separate negation for fused multiply-add */
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tcg_gen_xori_i32(tcg_ctx, tcg_op1, tcg_op1, 0x8000);
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read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
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fpst);
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break;
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case 0xa: /* FSUB */
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gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0xe: /* FMIN */
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gen_helper_advsimd_minh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0xf: /* FRSQRTS */
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gen_helper_rsqrtsf_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x13: /* FMUL */
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gen_helper_advsimd_mulh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x14: /* FCMGE */
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gen_helper_advsimd_cge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x15: /* FACGE */
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gen_helper_advsimd_acge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x17: /* FDIV */
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gen_helper_advsimd_divh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1a: /* FABD */
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gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0x7fff);
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break;
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case 0x1c: /* FCMGT */
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gen_helper_advsimd_cgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1d: /* FACGT */
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gen_helper_advsimd_acgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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default:
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fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
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__func__, insn, fpopcode, s->pc);
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g_assert_not_reached();
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read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
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read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
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tcg_res[pass] = tcg_temp_new_i32(tcg_ctx);
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switch (fpopcode) {
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case 0x10: /* FMAXNMP */
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gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2,
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fpst);
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break;
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case 0x12: /* FADDP */
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gen_helper_advsimd_addh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
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break;
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case 0x16: /* FMAXP */
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gen_helper_advsimd_maxh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
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break;
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case 0x18: /* FMINNMP */
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gen_helper_advsimd_minnumh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2,
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fpst);
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break;
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case 0x1e: /* FMINP */
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gen_helper_advsimd_minh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
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break;
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default:
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g_assert_not_reached();
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}
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}
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for (pass = 0; pass < maxpass; pass++) {
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write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
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tcg_temp_free_i32(tcg_ctx, tcg_res[pass]);
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}
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write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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tcg_temp_free_i32(tcg_ctx, tcg_res);
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tcg_temp_free_i32(tcg_ctx, tcg_op1);
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tcg_temp_free_i32(tcg_ctx, tcg_op2);
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} else {
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for (pass = 0; pass < elements; pass++) {
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TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
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read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
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switch (fpopcode) {
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case 0x0: /* FMAXNM */
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gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1: /* FMLA */
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read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
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fpst);
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break;
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case 0x2: /* FADD */
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gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3: /* FMULX */
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gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x4: /* FCMEQ */
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gen_helper_advsimd_ceq_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x6: /* FMAX */
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gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7: /* FRECPS */
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gen_helper_recpsf_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x8: /* FMINNM */
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gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x9: /* FMLS */
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/* As usual for ARM, separate negation for fused multiply-add */
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tcg_gen_xori_i32(tcg_ctx, tcg_op1, tcg_op1, 0x8000);
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read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res,
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fpst);
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break;
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case 0xa: /* FSUB */
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gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0xe: /* FMIN */
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gen_helper_advsimd_minh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0xf: /* FRSQRTS */
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gen_helper_rsqrtsf_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x13: /* FMUL */
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gen_helper_advsimd_mulh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x14: /* FCMGE */
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gen_helper_advsimd_cge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x15: /* FACGE */
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gen_helper_advsimd_acge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x17: /* FDIV */
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gen_helper_advsimd_divh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1a: /* FABD */
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gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0x7fff);
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break;
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case 0x1c: /* FCMGT */
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gen_helper_advsimd_cgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1d: /* FACGT */
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gen_helper_advsimd_acgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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default:
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fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
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__func__, insn, fpopcode, s->pc);
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g_assert_not_reached();
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}
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write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
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tcg_temp_free_i32(tcg_ctx, tcg_res);
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tcg_temp_free_i32(tcg_ctx, tcg_op1);
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tcg_temp_free_i32(tcg_ctx, tcg_op2);
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}
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}
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tcg_temp_free_ptr(tcg_ctx, fpst);
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