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target/mips: Extend gen_scwp() functionality to support EVA

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Extend gen_scwp() functionality to support EVA by adding an
additional argument, modify internals of the function to handle
new functionality, and accordingly change its invocations.

Backports commit 8d5388c1de8bf207316369213bd950bafa6badda from qemu
This commit is contained in:
Aleksandar Markovic 2019-01-25 12:46:45 -05:00 committed by Lioncash
parent 49e7e28ec9
commit dbeb82e424
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 4 deletions
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10
qemu/target/mips/translate.c
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@ -3729,7 +3729,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
uint32_t reg1, uint32_t reg2)
uint32_t reg1, uint32_t reg2, bool eva)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv taddr = tcg_temp_local_new(tcg_ctx);
@ -3758,7 +3758,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_ld_i64(tcg_ctx, llval, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(tcg_ctx, val, taddr, llval, tval,
ctx->mem_idx, MO_64);
eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
if (reg1 != 0) {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg1], 1);
}
@ -21683,7 +21683,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SCWP:
check_xnp(ctx);
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
}
break;
@ -21787,7 +21788,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
true);
break;
default:
generate_exception_end(ctx, EXCP_RI);