From dedab81d68d2def4365315a81435fb983625cb1e Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Mon, 26 Feb 2018 05:01:26 -0500 Subject: [PATCH] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Backports commit 173ff58580b383a7841b18fddb293038c9d40d1c from qemu --- qemu/target-arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c index e6ac1495..5be6d76e 100644 --- a/qemu/target-arm/translate-a64.c +++ b/qemu/target-arm/translate-a64.c @@ -2067,7 +2067,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) do_fp_ld(s, rt, tcg_addr, size); } else { /* Only unsigned 32bit loads target 32bit registers. */ - bool iss_sf = opc == 0 ? 32 : 64; + bool iss_sf = opc != 0; do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, true, rt, iss_sf, false);