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https://github.com/yuzu-emu/unicorn
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change uch to uc_struct (target-sparc)
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parent
15a774ac90
commit
e7a8eb8976
4 changed files with 13 additions and 21 deletions
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@ -2632,7 +2632,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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// Unicorn: trace this instruction on request
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if (dc->uc->hook_insn) {
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struct hook_struct *trace = hook_find((uch)dc->uc, UC_HOOK_CODE, dc->pc);
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struct hook_struct *trace = hook_find(dc->uc, UC_HOOK_CODE, dc->pc);
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if (trace)
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gen_uc_tracecode(tcg_ctx, 4, trace->callback, dc->uc, dc->pc, trace->user_data);
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// if requested to emulate only some instructions, check if
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@ -5406,7 +5406,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
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// Unicorn: trace this block on request
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if (env->uc->hook_block) {
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struct hook_struct *trace = hook_find((uch)env->uc, UC_HOOK_BLOCK, pc_start);
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struct hook_struct *trace = hook_find(env->uc, UC_HOOK_BLOCK, pc_start);
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if (trace) {
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// save block address to see if we need to patch block size later
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env->uc->block_addr = pc_start;
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@ -32,12 +32,10 @@ static void sparc_set_pc(struct uc_struct *uc, uint64_t address)
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((CPUSPARCState *)uc->current_cpu->env_ptr)->npc = address + 4;
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}
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void sparc_reg_reset(uch handle)
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void sparc_reg_reset(struct uc_struct *uc)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUArchState *env;
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CPUArchState *env = first_cpu->env_ptr;
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env = first_cpu->env_ptr;
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memset(env->gregs, 0, sizeof(env->gregs));
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memset(env->fpr, 0, sizeof(env->fpr));
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memset(env->regbase, 0, sizeof(env->regbase));
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@ -46,9 +44,8 @@ void sparc_reg_reset(uch handle)
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env->npc = 0;
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}
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int sparc_reg_read(uch handle, unsigned int regid, void *value)
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int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUState *mycpu = first_cpu;
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
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@ -71,9 +68,8 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
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#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
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#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
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int sparc_reg_write(uch handle, unsigned int regid, const void *value)
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int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUState *mycpu = first_cpu;
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
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@ -5,10 +5,10 @@
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#define UC_QEMU_TARGET_SPARC_H
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// functions to read & write registers
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int sparc_reg_read(uch handle, unsigned int regid, void *value);
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int sparc_reg_write(uch handle, unsigned int regid, const void *value);
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int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value);
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int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value);
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void sparc_reg_reset(uch handle);
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void sparc_reg_reset(struct uc_struct *uc);
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void sparc_uc_init(struct uc_struct* uc);
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void sparc64_uc_init(struct uc_struct* uc);
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@ -15,12 +15,10 @@
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#define READ_BYTE_L(x) (x & 0xff)
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void sparc_reg_reset(uch handle)
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void sparc_reg_reset(struct uc_struct *uc)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUArchState *env;
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CPUArchState *env = first_cpu->env_ptr;
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env = first_cpu->env_ptr;
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memset(env->gregs, 0, sizeof(env->gregs));
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memset(env->fpr, 0, sizeof(env->fpr));
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memset(env->regbase, 0, sizeof(env->regbase));
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@ -29,9 +27,8 @@ void sparc_reg_reset(uch handle)
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env->npc = 0;
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}
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int sparc_reg_read(uch handle, unsigned int regid, void *value)
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int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUState *mycpu = first_cpu;
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
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@ -54,9 +51,8 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
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#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
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#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
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int sparc_reg_write(uch handle, unsigned int regid, const void *value)
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int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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{
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struct uc_struct *uc = (struct uc_struct *) handle;
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CPUState *mycpu = first_cpu;
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
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