From e96282eb28c5fb80e576d2b5120c961f739e2b5f Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 19 Mar 2019 05:37:40 -0400 Subject: [PATCH] target/riscv: Remove decode_RV32_64G() decodetree handles all instructions now so the fallback is not necessary anymore. Backports commit 25e6ca30c668783cd72ff97080ff44e141b99f9b from qemu --- qemu/target/riscv/translate.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c index c62a87d0..1b78323a 100644 --- a/qemu/target/riscv/translate.c +++ b/qemu/target/riscv/translate.c @@ -673,24 +673,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" -static void decode_RV32_64G(DisasContext *ctx) -{ - uint32_t op; - - /* We do not do misaligned address check here: the address should never be - * misaligned at this point. Instructions that set PC must do the check, - * since epc must be the address of the instruction that caused us to - * perform the misaligned instruction fetch */ - - op = MASK_OP_MAJOR(ctx->opcode); - - switch (op) { - default: - gen_exception_illegal(ctx); - break; - } -} - static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ @@ -707,8 +689,7 @@ static void decode_opc(DisasContext *ctx) } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, ctx->opcode)) { - /* fallback to old decoder */ - decode_RV32_64G(ctx); + gen_exception_illegal(ctx); } } }