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target/arm: Fix do_predset for large VL

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Use MAKE_64BIT_MASK instead of open-coding. Remove an odd
vector size check that is unlikely to be more profitable
than 3 64-bit integer stores. Correct the iteration for WORD
to avoid writing too much data.

Fixes RISU tests of PTRUE for VL 256.

Backports commit 973558a3f869e591d2406dd8226ec0c4e32a3c3e from qemu
This commit is contained in:
Richard Henderson 2018-07-09 16:43:13 -04:00 committed by Lioncash
parent f1aaf5be62
commit ee24dff90c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 8 deletions
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10
qemu/target/arm/translate-sve.c
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@ -1535,7 +1535,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
setsz = numelem << esz;
lastword = word = pred_esz_masks[esz];
if (setsz % 64) {
lastword &= ~(-1ull << (setsz % 64));
lastword &= MAKE_64BIT_MASK(0, setsz % 64);
}
}
@ -1554,19 +1554,13 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
tcg_gen_gvec_dup64i(tcg_ctx, ofs, oprsz, maxsz, word);
goto done;
}
if (oprsz * 8 == setsz + 8) {
tcg_gen_gvec_dup64i(tcg_ctx, ofs, oprsz, maxsz, word);
tcg_gen_movi_i64(tcg_ctx, t, 0);
tcg_gen_st_i64(tcg_ctx, t, tcg_ctx->cpu_env, ofs + oprsz - 8);
goto done;
}
}
setsz /= 8;
fullsz /= 8;
tcg_gen_movi_i64(tcg_ctx, t, word);
for (i = 0; i < setsz; i += 8) {
for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
tcg_gen_st_i64(tcg_ctx, t, tcg_ctx->cpu_env, ofs + i);
}
if (lastword != word) {