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target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

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Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
AArch64 user mode emulation.

Backports commit 955f56d44a73d74016b2e71765d984ac7a6db1dc from qemu
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Ard Biesheuvel 2018-03-07 08:58:39 -05:00 committed by Lioncash
parent 85e6d710e4
commit f425b6aa81
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 0 deletions
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4
qemu/target/arm/cpu64.c
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@ -202,6 +202,10 @@ static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
}