mirrors-yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn synced 2024-11-24 10:18:09 +00:00
Code Issues Projects Releases Packages Wiki Activity

target/arm: Allow ARMv6-M Thumb2 instructions

Browse source 
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.

This patch is required for future Cortex-M0 support.

Backports commit 14120108f87b3f9e1beacdf0a6096e464e62bb65 from qemu
This commit is contained in:
Julia Suvorova 2018-06-15 14:12:12 -04:00 committed by Lioncash
parent d81cc5f5cd
commit f447a6f668
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 38 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

43
qemu/target/arm/translate.c
View file

@ -10134,7 +10134,8 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
* end up actually treating this as two 16-bit insns, though, * end up actually treating this as two 16-bit insns, though,
* if it's half of a bl/blx pair that might span a page boundary. * if it's half of a bl/blx pair that might span a page boundary.
*/ */
if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) { if (arm_dc_feature(s, ARM_FEATURE_THUMB2) ||
arm_dc_feature(s, ARM_FEATURE_M)) {
/* Thumb2 cores (including all M profile ones) always treat /* Thumb2 cores (including all M profile ones) always treat
* 32-bit insns as 32-bit. * 32-bit insns as 32-bit.
*/ */
@ -10256,10 +10257,38 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
int conds; int conds;
int logic_cc; int logic_cc;
/* The only 32 bit insn that's allowed for Thumb1 is the combined /*
* BL/BLX prefix and suffix. * ARMv6-M supports a limited subset of Thumb2 instructions.
* Other Thumb1 architectures allow only 32-bit
* combined BL/BLX prefix and suffix.
*/ */
if ((insn & 0xf800e800) != 0xf000e800) { if (arm_dc_feature(s, ARM_FEATURE_M) &&
!arm_dc_feature(s, ARM_FEATURE_V7)) {
int i;
bool found = false;
const uint32_t armv6m_insn[] = {0xf3808000 /* msr */,
0xf3b08040 /* dsb */,
0xf3b08050 /* dmb */,
0xf3b08060 /* isb */,
0xf3e08000 /* mrs */,
0xf000d000 /* bl */};
const uint32_t armv6m_mask[] = {0xffe0d000,
0xfff0d0f0,
0xfff0d0f0,
0xfff0d0f0,
0xffe0d000,
0xf800d000};
for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) {
if ((insn & armv6m_mask[i]) == armv6m_insn[i]) {
found = true;
break;
}
}
if (!found) {
goto illegal_op;
}
} else if ((insn & 0xf800e800) != 0xf000e800) {
ARCH(6T2); ARCH(6T2);
} }
@ -11180,7 +11209,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
} }
break; break;
case 3: /* Special control operations. */ case 3: /* Special control operations. */
ARCH(7); if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
!(arm_dc_feature(s, ARM_FEATURE_V6) &&
arm_dc_feature(s, ARM_FEATURE_M))) {
goto illegal_op;
}
op = (insn >> 4) & 0xf; op = (insn >> 4) & 0xf;
switch (op) { switch (op) {
case 2: /* clrex */ case 2: /* clrex */