From f90c819a33437dbf2e4dc47805df388a6e969f7c Mon Sep 17 00:00:00 2001 From: MerryMage Date: Thu, 11 Jan 2018 18:26:51 +0000 Subject: [PATCH] aarch64: Add pstate pseudoregister --- include/unicorn/arm64.h | 2 ++ qemu/target-arm/unicorn_aarch64.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index 40f76aa1..130d605e 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -290,6 +290,8 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_TPIDR_EL0, UC_ARM64_REG_TPIDRRO_EL0, UC_ARM64_REG_TPIDR_EL1, + + UC_ARM64_REG_PSTATE, // PSTATE pseudoregister UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index 45ce2b37..e255f306 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -106,6 +106,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co case UC_ARM64_REG_NZCV: *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV; break; + case UC_ARM64_REG_PSTATE: + *(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env); + break; } } } @@ -174,6 +177,9 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, case UC_ARM64_REG_NZCV: cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV); break; + case UC_ARM64_REG_PSTATE: + pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value); + break; } } }