diff --git a/qemu/include/exec/memory.h b/qemu/include/exec/memory.h
index bab1270a..6b2ee7e1 100644
--- a/qemu/include/exec/memory.h
+++ b/qemu/include/exec/memory.h
@@ -1160,9 +1160,11 @@ void *qemu_map_ram_ptr(struct uc_struct *uc, RAMBlock *ram_block,
 static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
 {
     if (is_write) {
-        return memory_region_is_ram(mr) && !mr->readonly;
+        return memory_region_is_ram(mr) &&
+               !mr->readonly && !memory_region_is_ram_device(mr);
     } else {
-        return memory_region_is_ram(mr) || memory_region_is_romd(mr);
+        return (memory_region_is_ram(mr) && !memory_region_is_ram_device(mr)) ||
+               memory_region_is_romd(mr);
     }
 }
 
diff --git a/qemu/memory.c b/qemu/memory.c
index 69504074..4707811d 100644
--- a/qemu/memory.c
+++ b/qemu/memory.c
@@ -1012,6 +1012,77 @@ const MemoryRegionOps unassigned_mem_ops = {
     {0,0,false,unassigned_mem_accepts},
 };
 
+static uint64_t memory_region_ram_device_read(struct uc_struct *uc,
+                                              void *opaque, hwaddr addr,
+                                              unsigned size)
+{
+    MemoryRegion *mr = opaque;
+    uint64_t data = (uint64_t)~0;
+
+    switch (size) {
+    case 1:
+        data = *(uint8_t *)(mr->ram_block->host + addr);
+        break;
+    case 2:
+        data = *(uint16_t *)(mr->ram_block->host + addr);
+        break;
+    case 4:
+        data = *(uint32_t *)(mr->ram_block->host + addr);
+        break;
+    case 8:
+        data = *(uint64_t *)(mr->ram_block->host + addr);
+        break;
+    }
+
+    // Unicorn: commented out
+    //trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
+
+    return data;
+}
+
+static void memory_region_ram_device_write(struct uc_struct *uc,
+                                           void *opaque, hwaddr addr,
+                                           uint64_t data, unsigned size)
+{
+    MemoryRegion *mr = opaque;
+
+    // Unicorn: commented out
+    //trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
+
+    switch (size) {
+    case 1:
+        *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
+        break;
+    case 2:
+        *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
+        break;
+    case 4:
+        *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
+        break;
+    case 8:
+        *(uint64_t *)(mr->ram_block->host + addr) = data;
+        break;
+    }
+}
+
+static const MemoryRegionOps ram_device_mem_ops = {
+    memory_region_ram_device_read,
+    memory_region_ram_device_write,
+    NULL,
+    NULL,
+    DEVICE_NATIVE_ENDIAN,
+    // valid
+    {
+        1, 8,
+        true,
+    },
+    // impl
+    {
+        1, 8,
+        true,
+    },
+};
+
 bool memory_region_access_valid(MemoryRegion *mr,
                                 hwaddr addr,
                                 unsigned size,
@@ -1221,6 +1292,8 @@ void memory_region_init_ram_device_ptr(struct uc_struct *uc,
 {
     memory_region_init_ram_ptr(uc, mr, owner, name, size, ptr);
     mr->ram_device = true;
+    mr->ops = &ram_device_mem_ops;
+    mr->opaque = mr;
 }
 
 void memory_region_init_alias(struct uc_struct *uc, MemoryRegion *mr,