mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-26 00:37:47 +00:00
b2f1326437
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
285 lines
7.3 KiB
C
285 lines
7.3 KiB
C
/*
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* Sparc64 interrupt helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
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CPUSPARCState *env = &cpu->env;
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int intno = cs->exception_index;
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trap_state *tsptr;
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/* Compute PSR before exposing state. */
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if (env->cc_op != CC_OP_FLAGS) {
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cpu_get_psr(env);
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}
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#if !defined(CONFIG_USER_ONLY)
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if (env->tl >= env->maxtl) {
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cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
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" Error state", cs->exception_index, env->tl, env->maxtl);
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return;
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}
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#endif
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if (env->tl < env->maxtl - 1) {
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env->tl++;
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} else {
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env->pstate |= PS_RED;
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if (env->tl < env->maxtl) {
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env->tl++;
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}
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}
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tsptr = cpu_tsptr(env);
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tsptr->tstate = (cpu_get_ccr(env) << 32) |
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((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
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cpu_get_cwp64(env);
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tsptr->tpc = env->pc;
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tsptr->tnpc = env->npc;
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tsptr->tt = intno;
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if (cpu_has_hypervisor(env)) {
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env->htstate[env->tl] = env->hpstate;
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/* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
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but this may change in the future */
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if (env->tl > 2) {
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env->hpstate |= HS_PRIV;
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}
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}
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if (env->def->features & CPU_FEATURE_GL) {
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tsptr->tstate |= (env->gl & 7ULL) << 40;
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cpu_gl_switch_gregs(env, env->gl + 1);
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env->gl++;
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}
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switch (intno) {
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case TT_IVEC:
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if (!cpu_has_hypervisor(env)) {
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
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}
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break;
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case TT_TFAULT:
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case TT_DFAULT:
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case TT_TMISS: case TT_TMISS+1: case TT_TMISS+2: case TT_TMISS+3:
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case TT_DMISS: case TT_DMISS+1: case TT_DMISS+2: case TT_DMISS+3:
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case TT_DPROT: case TT_DPROT+1: case TT_DPROT+2: case TT_DPROT+3:
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if (cpu_has_hypervisor(env)) {
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env->hpstate |= HS_PRIV;
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env->pstate = PS_PEF | PS_PRIV;
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} else {
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
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}
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break;
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case TT_INSN_REAL_TRANSLATION_MISS:
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case TT_DATA_REAL_TRANSLATION_MISS:
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case TT_HTRAP:
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case TT_HTRAP+1:
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case TT_HTRAP+2:
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case TT_HTRAP+3:
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case TT_HTRAP+4:
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case TT_HTRAP+5:
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case TT_HTRAP+6:
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case TT_HTRAP+7:
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case TT_HTRAP+8:
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case TT_HTRAP+9:
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case TT_HTRAP+10:
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case TT_HTRAP+11:
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case TT_HTRAP+12:
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case TT_HTRAP+13:
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case TT_HTRAP+14:
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case TT_HTRAP+15:
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case TT_HTRAP+16:
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case TT_HTRAP+17:
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case TT_HTRAP+18:
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case TT_HTRAP+19:
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case TT_HTRAP+20:
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case TT_HTRAP+21:
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case TT_HTRAP+22:
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case TT_HTRAP+23:
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case TT_HTRAP+24:
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case TT_HTRAP+25:
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case TT_HTRAP+26:
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case TT_HTRAP+27:
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case TT_HTRAP+28:
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case TT_HTRAP+29:
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case TT_HTRAP+30:
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case TT_HTRAP+31:
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case TT_HTRAP+32:
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case TT_HTRAP+33:
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case TT_HTRAP+34:
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case TT_HTRAP+35:
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case TT_HTRAP+36:
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case TT_HTRAP+37:
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case TT_HTRAP+38:
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case TT_HTRAP+39:
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case TT_HTRAP+40:
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case TT_HTRAP+41:
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case TT_HTRAP+42:
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case TT_HTRAP+43:
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case TT_HTRAP+44:
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case TT_HTRAP+45:
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case TT_HTRAP+46:
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case TT_HTRAP+47:
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case TT_HTRAP+48:
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case TT_HTRAP+49:
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case TT_HTRAP+50:
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case TT_HTRAP+51:
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case TT_HTRAP+52:
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case TT_HTRAP+53:
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case TT_HTRAP+54:
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case TT_HTRAP+55:
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case TT_HTRAP+56:
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case TT_HTRAP+57:
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case TT_HTRAP+58:
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case TT_HTRAP+59:
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case TT_HTRAP+60:
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case TT_HTRAP+61:
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case TT_HTRAP+62:
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case TT_HTRAP+63:
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case TT_HTRAP+64:
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case TT_HTRAP+65:
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case TT_HTRAP+66:
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case TT_HTRAP+67:
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case TT_HTRAP+68:
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case TT_HTRAP+69:
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case TT_HTRAP+70:
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case TT_HTRAP+71:
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case TT_HTRAP+72:
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case TT_HTRAP+73:
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case TT_HTRAP+74:
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case TT_HTRAP+75:
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case TT_HTRAP+76:
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case TT_HTRAP+77:
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case TT_HTRAP+78:
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case TT_HTRAP+79:
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case TT_HTRAP+80:
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case TT_HTRAP+81:
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case TT_HTRAP+82:
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case TT_HTRAP+83:
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case TT_HTRAP+84:
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case TT_HTRAP+85:
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case TT_HTRAP+86:
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case TT_HTRAP+87:
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case TT_HTRAP+88:
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case TT_HTRAP+89:
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case TT_HTRAP+90:
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case TT_HTRAP+91:
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case TT_HTRAP+92:
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case TT_HTRAP+93:
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case TT_HTRAP+94:
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case TT_HTRAP+95:
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case TT_HTRAP+96:
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case TT_HTRAP+97:
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case TT_HTRAP+98:
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case TT_HTRAP+99:
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case TT_HTRAP+100:
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case TT_HTRAP+101:
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case TT_HTRAP+102:
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case TT_HTRAP+103:
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case TT_HTRAP+104:
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case TT_HTRAP+105:
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case TT_HTRAP+106:
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case TT_HTRAP+107:
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case TT_HTRAP+108:
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case TT_HTRAP+109:
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case TT_HTRAP+110:
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case TT_HTRAP+111:
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case TT_HTRAP+112:
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case TT_HTRAP+113:
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case TT_HTRAP+114:
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case TT_HTRAP+115:
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case TT_HTRAP+116:
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case TT_HTRAP+117:
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case TT_HTRAP+118:
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case TT_HTRAP+119:
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case TT_HTRAP+120:
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case TT_HTRAP+121:
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case TT_HTRAP+122:
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case TT_HTRAP+123:
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case TT_HTRAP+124:
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case TT_HTRAP+125:
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case TT_HTRAP+126:
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case TT_HTRAP+127:
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env->hpstate |= HS_PRIV;
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default:
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
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break;
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}
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if (intno == TT_CLRWIN) {
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
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} else if ((intno & 0x1c0) == TT_SPILL) {
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
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} else if ((intno & 0x1c0) == TT_FILL) {
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cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
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}
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if (cpu_hypervisor_mode(env)) {
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env->pc = (env->htba & ~0x3fffULL) | (intno << 5);
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} else {
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env->pc = env->tbr & ~0x7fffULL;
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env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
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}
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env->npc = env->pc + 4;
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cs->exception_index = -1;
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}
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trap_state *cpu_tsptr(CPUSPARCState* env)
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{
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return &env->ts[env->tl & MAXTL_MASK];
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}
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static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
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{
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if (env->softint != value) {
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env->softint = value;
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#if !defined(CONFIG_USER_ONLY)
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if (cpu_interrupts_enabled(env)) {
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//cpu_check_irqs(env);
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}
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#endif
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return true;
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}
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return false;
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}
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void helper_set_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, env->softint | (uint32_t)value)) {
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//trace_int_helper_set_softint(env->softint);
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}
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}
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void helper_clear_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
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//trace_int_helper_clear_softint(env->softint);
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}
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}
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void helper_write_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, (uint32_t)value)) {
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//trace_int_helper_write_softint(env->softint);
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}
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}
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