mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 15:19:00 +00:00
b2f1326437
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* Sparc32 interrupt helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "sysemu/sysemu.h"
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
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CPUSPARCState *env = &cpu->env;
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int cwp, intno = cs->exception_index;
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/* Compute PSR before exposing state. */
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if (env->cc_op != CC_OP_FLAGS) {
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cpu_get_psr(env);
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}
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#if !defined(CONFIG_USER_ONLY)
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if (env->psret == 0) {
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if (cs->exception_index == 0x80 &&
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env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
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qemu_system_shutdown_request();
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} else {
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cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
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cs->exception_index);
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}
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return;
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}
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#endif
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env->psret = 0;
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cwp = cpu_cwp_dec(env, env->cwp - 1);
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cpu_set_cwp(env, cwp);
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env->regwptr[9] = env->pc;
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env->regwptr[10] = env->npc;
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env->psrps = env->psrs;
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env->psrs = 1;
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env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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cs->exception_index = -1;
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}
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#if !defined(CONFIG_USER_ONLY)
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static void leon3_cache_control_int(CPUSPARCState *env)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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//trace_int_helper_icache_freeze();
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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//trace_int_helper_dcache_freeze();
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}
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env->cache_control &= ~(CACHE_STATE_MASK << 2);
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env->cache_control |= (state << 2);
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}
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}
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void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
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{
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//leon3_irq_ack(irq_manager, intno);
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leon3_cache_control_int(env);
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}
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#endif
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