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https://github.com/yuzu-emu/unicorn
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0eee5afd0e
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Backports commit 24f91e81b65fcdd0552d1f0fcb0ea7cfe3829c19 from qemu
621 lines
20 KiB
C
621 lines
20 KiB
C
/*
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* AArch64 specific helpers
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "qemu/log.h"
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#include "sysemu/sysemu.h"
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#include "qemu/bitops.h"
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#include "internals.h"
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#include "qemu/crc32c.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/int128.h"
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#include "tcg.h"
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#include "fpu/softfloat.h"
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/* C2.4.7 Multiply and divide */
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/* special cases for 0 and LLONG_MIN are mandated by the standard */
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uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
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{
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if (den == 0) {
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return 0;
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}
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return num / den;
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}
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int64_t HELPER(sdiv64)(int64_t num, int64_t den)
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{
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if (den == 0) {
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return 0;
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}
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if (num == LLONG_MIN && den == -1) {
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return LLONG_MIN;
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}
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return num / den;
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}
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uint64_t HELPER(rbit64)(uint64_t x)
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{
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return revbit64(x);
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}
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/* Convert a softfloat float_relation_ (as returned by
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* the float*_compare functions) to the correct ARM
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* NZCV flag state.
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*/
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static inline uint32_t float_rel_to_flags(int res)
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{
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uint64_t flags;
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switch (res) {
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case float_relation_equal:
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flags = PSTATE_Z | PSTATE_C;
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break;
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case float_relation_less:
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flags = PSTATE_N;
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break;
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case float_relation_greater:
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flags = PSTATE_C;
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break;
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case float_relation_unordered:
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default:
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flags = PSTATE_C | PSTATE_V;
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break;
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}
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return flags;
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}
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uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
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{
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return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
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{
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return float_rel_to_flags(float32_compare(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
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{
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return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
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{
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return float_rel_to_flags(float64_compare(x, y, fp_status));
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}
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float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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if ((float32_is_zero(a) && float32_is_infinity(b)) ||
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(float32_is_infinity(a) && float32_is_zero(b))) {
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/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
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return make_float32((1U << 30) |
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((float32_val(a) ^ float32_val(b)) & (1U << 31)));
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}
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return float32_mul(a, b, fpst);
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}
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float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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if ((float64_is_zero(a) && float64_is_infinity(b)) ||
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(float64_is_infinity(a) && float64_is_zero(b))) {
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/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
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return make_float64((1ULL << 62) |
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((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
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}
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return float64_mul(a, b, fpst);
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}
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uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
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uint32_t rn, uint32_t numregs)
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{
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/* Helper function for SIMD TBL and TBX. We have to do the table
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* lookup part for the 64 bits worth of indices we're passed in.
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* result is the initial results vector (either zeroes for TBL
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* or some guest values for TBX), rn the register number where
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* the table starts, and numregs the number of registers in the table.
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* We return the results of the lookups.
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*/
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int shift;
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for (shift = 0; shift < 64; shift += 8) {
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int index = extract64(indices, shift, 8);
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if (index < 16 * numregs) {
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/* Convert index (a byte offset into the virtual table
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* which is a series of 128-bit vectors concatenated)
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* into the correct register element plus a bit offset
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* into that element, bearing in mind that the table
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* can wrap around from V31 to V0.
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*/
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int elt = (rn * 2 + (index >> 3)) % 64;
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int bitidx = (index & 7) * 8;
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uint64_t *q = aa64_vfp_qreg(env, elt >> 1);
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uint64_t val = extract64(q[elt & 1], bitidx, 8);
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result = deposit64(result, shift, 8, val);
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}
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}
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return result;
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}
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/* 64bit/double versions of the neon float compare functions */
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uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_eq_quiet(a, b, fpst);
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}
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uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_le(b, a, fpst);
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}
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uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_lt(b, a, fpst);
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}
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/* Reciprocal step and sqrt step. Note that unlike the A32/T32
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* versions, these do a fully fused multiply-add or
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* multiply-add-and-halve.
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*/
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#define float32_two make_float32(0x40000000)
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#define float32_three make_float32(0x40400000)
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#define float32_one_point_five make_float32(0x3fc00000)
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#define float64_two make_float64(0x4000000000000000ULL)
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#define float64_three make_float64(0x4008000000000000ULL)
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#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
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float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float32_squash_input_denormal(a, fpst);
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b = float32_squash_input_denormal(b, fpst);
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a = float32_chs(a);
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if ((float32_is_infinity(a) && float32_is_zero(b)) ||
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(float32_is_infinity(b) && float32_is_zero(a))) {
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return float32_two;
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}
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return float32_muladd(a, b, float32_two, 0, fpst);
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}
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float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float64_squash_input_denormal(a, fpst);
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b = float64_squash_input_denormal(b, fpst);
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a = float64_chs(a);
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if ((float64_is_infinity(a) && float64_is_zero(b)) ||
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(float64_is_infinity(b) && float64_is_zero(a))) {
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return float64_two;
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}
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return float64_muladd(a, b, float64_two, 0, fpst);
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}
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float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float32_squash_input_denormal(a, fpst);
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b = float32_squash_input_denormal(b, fpst);
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a = float32_chs(a);
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if ((float32_is_infinity(a) && float32_is_zero(b)) ||
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(float32_is_infinity(b) && float32_is_zero(a))) {
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return float32_one_point_five;
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}
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return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
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}
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float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float64_squash_input_denormal(a, fpst);
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b = float64_squash_input_denormal(b, fpst);
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a = float64_chs(a);
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if ((float64_is_infinity(a) && float64_is_zero(b)) ||
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(float64_is_infinity(b) && float64_is_zero(a))) {
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return float64_one_point_five;
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}
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return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
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}
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/* Pairwise long add: add pairs of adjacent elements into
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* double-width elements in the result (eg _s8 is an 8x8->16 op)
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*/
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uint64_t HELPER(neon_addlp_s8)(uint64_t a)
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{
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uint64_t nsignmask = 0x0080008000800080ULL;
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uint64_t wsignmask = 0x8000800080008000ULL;
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uint64_t elementmask = 0x00ff00ff00ff00ffULL;
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uint64_t tmp1, tmp2;
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uint64_t res, signres;
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/* Extract odd elements, sign extend each to a 16 bit field */
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tmp1 = a & elementmask;
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tmp1 ^= nsignmask;
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tmp1 |= wsignmask;
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tmp1 = (tmp1 - nsignmask) ^ wsignmask;
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/* Ditto for the even elements */
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tmp2 = (a >> 8) & elementmask;
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tmp2 ^= nsignmask;
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tmp2 |= wsignmask;
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tmp2 = (tmp2 - nsignmask) ^ wsignmask;
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/* calculate the result by summing bits 0..14, 16..22, etc,
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* and then adjusting the sign bits 15, 23, etc manually.
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* This ensures the addition can't overflow the 16 bit field.
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*/
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signres = (tmp1 ^ tmp2) & wsignmask;
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res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
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res ^= signres;
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return res;
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}
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uint64_t HELPER(neon_addlp_u8)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x00ff00ff00ff00ffULL;
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tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
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return tmp;
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}
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uint64_t HELPER(neon_addlp_s16)(uint64_t a)
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{
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int32_t reslo, reshi;
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reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
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reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
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return (uint32_t)reslo | (((uint64_t)reshi) << 32);
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}
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uint64_t HELPER(neon_addlp_u16)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x0000ffff0000ffffULL;
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tmp += (a >> 16) & 0x0000ffff0000ffffULL;
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return tmp;
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}
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/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
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float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
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{
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float_status *fpst = fpstp;
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uint32_t val32, sbit;
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int32_t exp;
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if (float32_is_any_nan(a)) {
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float32 nan = a;
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if (float32_is_signaling_nan(a, fpst)) {
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float_raise(float_flag_invalid, fpst);
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nan = float32_maybe_silence_nan(a, fpst);
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}
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if (fpst->default_nan_mode) {
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nan = float32_default_nan(fpst);
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}
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return nan;
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}
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val32 = float32_val(a);
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sbit = 0x80000000ULL & val32;
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exp = extract32(val32, 23, 8);
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if (exp == 0) {
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return make_float32(sbit | (0xfe << 23));
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} else {
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return make_float32(sbit | (~exp & 0xff) << 23);
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}
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}
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float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
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{
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float_status *fpst = fpstp;
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uint64_t val64, sbit;
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int64_t exp;
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if (float64_is_any_nan(a)) {
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float64 nan = a;
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if (float64_is_signaling_nan(a, fpst)) {
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float_raise(float_flag_invalid, fpst);
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nan = float64_maybe_silence_nan(a, fpst);
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}
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if (fpst->default_nan_mode) {
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nan = float64_default_nan(fpst);
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}
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return nan;
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}
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val64 = float64_val(a);
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sbit = 0x8000000000000000ULL & val64;
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exp = extract64(float64_val(a), 52, 11);
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if (exp == 0) {
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return make_float64(sbit | (0x7feULL << 52));
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} else {
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return make_float64(sbit | (~exp & 0x7ffULL) << 52);
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}
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}
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float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
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{
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/* Von Neumann rounding is implemented by using round-to-zero
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* and then setting the LSB of the result if Inexact was raised.
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*/
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float32 r;
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float_status *fpst = &env->vfp.fp_status;
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float_status tstat = *fpst;
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int exflags;
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set_float_rounding_mode(float_round_to_zero, &tstat);
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set_float_exception_flags(0, &tstat);
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r = float64_to_float32(a, &tstat);
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r = float32_maybe_silence_nan(r, fpst);
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exflags = get_float_exception_flags(&tstat);
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if (exflags & float_flag_inexact) {
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r = make_float32(float32_val(r) | 1);
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}
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exflags |= get_float_exception_flags(fpst);
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set_float_exception_flags(exflags, fpst);
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return r;
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}
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/* 64-bit versions of the CRC helpers. Note that although the operation
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* (and the prototypes of crc32c() and crc32() mean that only the bottom
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* 32 bits of the accumulator and result are used, we pass and return
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* uint64_t for convenience of the generated code. Unlike the 32-bit
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* instruction set versions, val may genuinely have 64 bits of data in it.
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* The upper bytes of val (above the number specified by 'bytes') must have
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* been zeroed out by the caller.
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*/
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uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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{
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uint8_t buf[8];
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stq_le_p(buf, val);
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static const uint32_t iso_table[256] = {
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0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
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0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
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0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
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0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
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0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
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0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
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0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
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0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
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0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
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0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
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0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
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0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
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0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
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0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
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0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
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0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
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0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
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0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
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0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
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0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
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0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
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0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
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|
0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
|
|
0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
|
|
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
|
|
0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
|
|
0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
|
|
0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
|
|
0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
|
|
0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
|
|
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
|
|
0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
|
|
0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
|
|
0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
|
|
0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
|
|
0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
|
|
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
|
|
0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
|
|
0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
|
|
0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
|
|
0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
|
|
0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
|
|
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
|
|
0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
|
|
0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
|
|
0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
|
|
0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
|
|
0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
|
|
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
|
|
0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
|
|
0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
|
|
0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
|
|
0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
|
|
0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
|
|
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
|
|
0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
|
|
0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
|
|
0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
|
|
0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
|
|
0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
|
|
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
|
|
0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
|
|
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
|
|
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
|
|
};
|
|
|
|
const uint8_t* data = buf;
|
|
uint32_t crc = (uint32_t)acc;
|
|
|
|
while (bytes-- > 0) {
|
|
crc = (crc >> 8) ^ iso_table[(crc ^ (*data++)) & 0xFF];
|
|
}
|
|
|
|
return crc;
|
|
|
|
/* zlib crc32 converts the accumulator and output to one's complement. */
|
|
// return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
|
|
}
|
|
|
|
uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
|
|
{
|
|
uint8_t buf[8];
|
|
|
|
stq_le_p(buf, val);
|
|
|
|
/* Linux crc32c converts the output to one's complement. */
|
|
return crc32c(acc, buf, bytes) ^ 0xffffffff;
|
|
}
|
|
|
|
/* Returns 0 on success; 1 otherwise. */
|
|
uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
|
|
uint64_t new_lo, uint64_t new_hi)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
Int128 oldv, cmpv, newv;
|
|
bool success;
|
|
|
|
/* high and low need to be switched here because this is not actually a
|
|
* 128bit store but two doublewords stored consecutively
|
|
*/
|
|
cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
|
|
newv = int128_make128(new_hi, new_lo);
|
|
|
|
if (env->uc->parallel_cpus) {
|
|
#ifndef CONFIG_ATOMIC128
|
|
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
|
|
#else
|
|
int mem_idx = cpu_mmu_index(env, false);
|
|
TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
|
|
oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
|
|
success = int128_eq(oldv, cmpv);
|
|
#endif
|
|
} else {
|
|
uint64_t o0, o1;
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* ??? Enforce alignment. */
|
|
uint64_t *haddr = g2h(addr);
|
|
|
|
env->uc->helper_retaddr = ra;
|
|
|
|
o0 = ldq_le_p(haddr + 0);
|
|
o1 = ldq_le_p(haddr + 1);
|
|
oldv = int128_make128(o0, o1);
|
|
|
|
success = int128_eq(oldv, cmpv);
|
|
if (success) {
|
|
stq_le_p(haddr + 0, int128_getlo(newv));
|
|
stq_le_p(haddr + 1, int128_gethi(newv));
|
|
}
|
|
env->uc->helper_retaddr = 0;
|
|
#else
|
|
int mem_idx = cpu_mmu_index(env, false);
|
|
TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
|
|
TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
|
|
|
|
o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
|
|
o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
|
|
oldv = int128_make128(o0, o1);
|
|
|
|
success = int128_eq(oldv, cmpv);
|
|
if (success) {
|
|
helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
|
|
helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return !success;
|
|
}
|
|
|
|
uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
|
|
uint64_t new_lo, uint64_t new_hi)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
Int128 oldv, cmpv, newv;
|
|
bool success;
|
|
|
|
cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
|
|
newv = int128_make128(new_lo, new_hi);
|
|
|
|
if (env->uc->parallel_cpus) {
|
|
#ifndef CONFIG_ATOMIC128
|
|
cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
|
|
#else
|
|
int mem_idx = cpu_mmu_index(env, false);
|
|
TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
|
|
oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
|
|
success = int128_eq(oldv, cmpv);
|
|
#endif
|
|
} else {
|
|
uint64_t o0, o1;
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* ??? Enforce alignment. */
|
|
uint64_t *haddr = g2h(addr);
|
|
|
|
env->uc->helper_retaddr = ra;
|
|
|
|
o1 = ldq_be_p(haddr + 0);
|
|
o0 = ldq_be_p(haddr + 1);
|
|
oldv = int128_make128(o0, o1);
|
|
|
|
success = int128_eq(oldv, cmpv);
|
|
if (success) {
|
|
stq_be_p(haddr + 0, int128_gethi(newv));
|
|
stq_be_p(haddr + 1, int128_getlo(newv));
|
|
}
|
|
env->uc->helper_retaddr = 0;
|
|
#else
|
|
int mem_idx = cpu_mmu_index(env, false);
|
|
TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
|
|
TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
|
|
|
|
o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
|
|
o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
|
|
oldv = int128_make128(o0, o1);
|
|
|
|
success = int128_eq(oldv, cmpv);
|
|
if (success) {
|
|
helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
|
|
helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return !success;
|
|
}
|
|
|