Michael Davidsaver 2769c6ada0 armv7m: Fix reads of CONTROL register bit 1 ... The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Backports commit abc24d86cc0364f402e438fae3acb14289b40734 from qemu		2018-03-02 13:26:38 -05:00
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arm	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
cpu
i386	Clean up decorations and whitespace around header guards	2018-02-25 04:26:02 -05:00
m68k
mips
sparc
xen
boards.h	cpu: Support a target CPU having a variable page size	2018-02-26 12:29:08 -05:00
hw.h	hw: clean up hw/hw.h includes	2018-02-24 02:46:41 -05:00
qdev-core.h	target-i386: Add x86_cpu_unrealizefn()	2018-02-25 20:54:13 -05:00
qdev.h
registerfields.h	armv7m: Fix reads of CONTROL register bit 1	2018-03-02 13:26:38 -05:00