mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-24 10:38:18 +00:00
311 lines
8.9 KiB
C
311 lines
8.9 KiB
C
/**
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* Unicorn x86_32 self-modifying unit test
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*
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* This test demonstrates the flushing of instruction translation cache
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* after a self-modification of Intel's x8's "IMUL Gv,Ev,Ib" instruction.
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*/
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#include "unicorn_test.h"
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#include <errno.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#define RIP_NEXT_TO_THE_SELFMODIFY_OPCODE (1)
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// Demostration of a self-modifying "IMUL eax,mem,Ib" opcode
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// And the QEMU's ability to flush the translation buffer properly
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#define MIN(a, b) (a < b? a: b)
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#define CODE_SPACE (2 * 1024 * 1024)
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#define PHY_STACK_REGION (0x60000000)
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#define X86_CODE32_ALPHA_MIXED \
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"\x89\xe1\xd9\xcd\xd9\x71\xf4\x5d\x55\x59\x49\x49\x49\x49\x49\x49" \
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"\x49\x49\x49\x49\x43\x43\x43\x43\x43\x43\x37\x51\x5a\x6a\x41\x58" \
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"\x50\x30\x41\x30\x41\x6b\x41\x41\x51\x32\x41\x42\x32\x42\x42\x30" \
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"\x42\x42\x41\x42\x58\x50\x38\x41\x42\x75\x4a\x49\x51\x51\x51\x52" \
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"\x47\x33\x47\x34\x51\x55\x51\x56\x50\x47\x47\x38\x47\x39\x50\x4a" \
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"\x50\x4b\x50\x4c\x50\x4d\x50\x4e\x50\x4f\x50\x50\x50\x31\x47\x42" \
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"\x47\x42\x50\x34\x50\x5a\x50\x45\x51\x52\x46\x32\x47\x31\x50\x4d" \
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"\x51\x51\x50\x4e\x41\x41"
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/* Called before every test to set up a new instance */
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static int setup(void **state)
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{
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uc_engine *uc;
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uc_assert_success(uc_open(UC_ARCH_X86, UC_MODE_64, &uc));
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*state = uc;
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return 0;
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}
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/* Called after every test to clean up */
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static int teardown(void **state)
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{
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uc_engine *uc = *state;
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uc_assert_success(uc_close(uc));
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*state = NULL;
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return 0;
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}
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static void dump_stack_mem(uc_engine *uc)
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{
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uint8_t tmp[256];
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uint32_t size;
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size = sizeof(X86_CODE32_ALPHA_MIXED);
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if (size > 255) size = 255;
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if (!uc_mem_read(uc, PHY_STACK_REGION, tmp, size))
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{
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uint32_t i;
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printf("Stack region dump");
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for (i=0; i<size; i++) {
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if ((i % 16) == 0) printf("\n%x: ", PHY_STACK_REGION+i);
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printf("%x ", tmp[i]);
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}
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printf("\n");
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}
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}
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static void print_registers(uc_engine *uc)
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{
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int32_t eax, ecx, edx, ebx;
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int32_t esp, ebp, esi, edi;
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uc_reg_read(uc, UC_X86_REG_EAX, &eax);
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uc_reg_read(uc, UC_X86_REG_ECX, &ecx);
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uc_reg_read(uc, UC_X86_REG_EDX, &edx);
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uc_reg_read(uc, UC_X86_REG_EBX, &ebx);
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uc_reg_read(uc, UC_X86_REG_ESP, &esp);
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uc_reg_read(uc, UC_X86_REG_EBP, &ebp);
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uc_reg_read(uc, UC_X86_REG_ESI, &esi);
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uc_reg_read(uc, UC_X86_REG_EDI, &edi);
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printf("Register dump:\n");
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printf("eax %8.8x ", eax);
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printf("ecx %8.8x ", ecx);
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printf("edx %8.8x ", edx);
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printf("ebx %8.8x\n", ebx);
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printf("esp %8.8x ", esp);
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printf("ebp %8.8x ", ebp);
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printf("esi %8.8x ", esi);
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printf("edi %8.8x ", edi);
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printf("\n");
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}
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static void hook_code32(uc_engine *uc,
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uint64_t address,
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uint32_t size,
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void *user_data)
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{
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//uint8_t opcode[256];
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uint8_t tmp[16];
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uint32_t tmp4[1];
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uint32_t ecx;
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printf("\nhook_code32: Address: %"PRIx64", Opcode Size: %d\n", address, size);
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print_registers(uc);
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size = MIN(sizeof(tmp), size);
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if (!uc_mem_read(uc, address, tmp, size))
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{
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uint32_t i;
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printf("Opcode: ");
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for (i=0; i<size; i++) {
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printf("%x ", tmp[i]);
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}
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printf("\n");
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}
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dump_stack_mem(uc);
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if (address == 0x60000025)
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{
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// double-check that opcode is
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// IMUL aex,[eax+0x41],0x10
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if ((tmp[0] != 0x6b) ||
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(tmp[1] != 0x41) ||
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(tmp[2] != 0x41) ||
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(tmp[3] != 0x10))
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{
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printf("FAILED set-up of opcode\n");
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exit(-1);
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}
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printf("IMUL eax,[ecx+0x41],0x10\n");
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// double-check that memory operand points to 0x6000003a
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uc_reg_read(uc, UC_X86_REG_ECX, &ecx);
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if (ecx != 0x5ffffff9)
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{
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printf("FAILED EAX register not having 0x5ffffff9\n");
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exit(-1);
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}
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printf("EAX = %8.8x\n", ecx);
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printf("%8.8x + 0x41 = %8.8x\n", 0x5ffffff9, 0x5ffffff9 + 0x41);
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// double-check that memory location 0x60000039
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// contains 0x5151494a
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if (!uc_mem_read(uc, 0x6000003a, tmp4, 4))
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{
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if (tmp4[0] != 0x5151494a)
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{
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printf("FAILED set-up\n");
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exit(-1);
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}
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printf("Proved that 0x6000003a contains the proper 0x5151494a\n");
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}
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// dump_stack_mem(uc);
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}
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// Stop after 'imul eax,[ecx+0x41],0x10
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if (address == 0x60000029)
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{
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uint32_t eax;
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// IMUL eax,mem,Ib
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// mem = [ecx+0x41]
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// ecx = 0x5ffffff9
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// [6000003A] = 0x5151494a
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// Stop after 'imul eax,[ecx+0x41],0x10
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// This step basically shifts left 8-bit...elaborately.
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// multiplying 0x5151494a x 0x10 = 0x151494a0
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uc_reg_read(uc, UC_X86_REG_EAX, &eax);
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if (eax != 0x151494a0)
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{
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fail_msg("FAIL: TB did not flush; eax is not the expected 0x151494a0\n");
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print_registers(uc);
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//dump_stack_mem(uc);
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exit(-1);
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}
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printf("PASS\n");
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}
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print_registers(uc);
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// dump_stack_mem(uc);
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return;
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}
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static void hook_mem32(uc_engine *uc,
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uc_mem_type type,
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uint64_t address,
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int size,
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uint64_t value,
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void *user_data)
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{
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char ctype;
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//uint32_t tmp[1];
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ctype = '?';
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if (type == UC_MEM_READ) ctype = 'R';
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if (type == UC_MEM_WRITE) ctype = 'W';
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printf("hook_mem32(%c): Address: 0x%"PRIx64", Size: %d, Value:0x%"PRIx64"\n", ctype, address, size, value);
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// if (!uc_mem_read(uc, 0x6000003a, tmp, 4))
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// {
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// printf(" hook_mem32 0x6000003a: %8.8x\n", tmp[0]);
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// }
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return;
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}
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static void test_tb_x86_64_32_imul_Gv_Ev_Ib(void **state)
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{
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uc_engine *uc = *state;
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uc_hook trace1, trace2;
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void *mem;
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#ifdef RIP_NEXT_TO_THE_SELFMODIFY_OPCODE
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// These values assumes just before PC = 0x60000021
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int64_t eax = 0x00000041;
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int64_t ecx = 0x5ffffff8;
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int64_t edx = 0x5ffffff8;
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int64_t ebx = 0x034a129b;
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int64_t esp = 0x6010229a;
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int64_t ebp = 0x60000002;
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int64_t esi = 0x1f350211;
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int64_t edi = 0x488ac239;
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#else
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// These values assumes PC == 0x6000000
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int64_t eax = 0x73952c43;
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int64_t ecx = 0x6010229a;
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int64_t edx = 0x2a500e50;
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int64_t ebx = 0x034a1295;
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int64_t esp = 0x6010229a;
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int64_t ebp = 0x60000000;
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int64_t esi = 0x1f350211;
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int64_t edi = 0x488ac239;
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#endif
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mem = calloc(1, CODE_SPACE);
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assert_int_not_equal(0, mem);
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uc_assert_success(uc_open(UC_ARCH_X86,
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UC_MODE_32,
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&uc));
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uc_assert_success(uc_mem_map(uc,
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PHY_STACK_REGION,
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CODE_SPACE,
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UC_PROT_ALL));
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uc_assert_success(uc_mem_write(uc,
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PHY_STACK_REGION,
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X86_CODE32_ALPHA_MIXED,
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sizeof(X86_CODE32_ALPHA_MIXED) - 1));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_EAX, &eax));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_ECX, &ecx));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_EDX, &edx));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_EBX, &ebx));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_ESP, &esp));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_EBP, &ebp));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_ESI, &esi));
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uc_assert_success(uc_reg_write(uc, UC_X86_REG_EDI, &edi));
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uc_assert_success(uc_hook_add(uc,
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&trace1,
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UC_HOOK_CODE,
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hook_code32,
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NULL,
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(uint64_t)1,
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(uint64_t)0));
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uc_assert_success(uc_hook_add(uc,
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&trace2,
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UC_HOOK_MEM_READ | UC_HOOK_MEM_WRITE | UC_HOOK_MEM_FETCH,
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hook_mem32,
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NULL,
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(uint64_t)1,
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(uint64_t)0));
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uc_assert_success(uc_emu_start(uc,
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#ifdef RIP_NEXT_TO_THE_SELFMODIFY_OPCODE
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// Register set (before self-modifying IMUL opcode)
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// Start at "0x00000021: xorb %al, 0x30(%ecx)
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// Start at "0x00000021: xor byte ptr [ecx + 0x30], al
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PHY_STACK_REGION+0x0021, // 0x0024 didn't work
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#else
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PHY_STACK_REGION+0x0000,
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#endif
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PHY_STACK_REGION+sizeof(X86_CODE32_ALPHA_MIXED) - 1,
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0, 0));
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uc_assert_success(uc_close(uc));
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}
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int
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main(void)
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{
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#define test(x) cmocka_unit_test_setup_teardown(x, setup, teardown)
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const struct CMUnitTest tests[] = {
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test(test_tb_x86_64_32_imul_Gv_Ev_Ib)
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};
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#undef test
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return cmocka_run_group_tests(tests, NULL, NULL);
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}
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