mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 20:28:16 +00:00
178 lines
5.5 KiB
C
178 lines
5.5 KiB
C
/*
|
|
* Tiny Code Generator for QEMU
|
|
*
|
|
* Copyright (c) 2008 Fabrice Bellard
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
* in the Software without restriction, including without limitation the rights
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
* furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
* THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef SPARC_TCG_TARGET_H
|
|
#define SPARC_TCG_TARGET_H
|
|
|
|
#define TCG_TARGET_REG_BITS 64
|
|
|
|
#define TCG_TARGET_INSN_UNIT_SIZE 4
|
|
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
|
|
#define TCG_TARGET_NB_REGS 32
|
|
|
|
typedef enum {
|
|
TCG_REG_G0 = 0,
|
|
TCG_REG_G1,
|
|
TCG_REG_G2,
|
|
TCG_REG_G3,
|
|
TCG_REG_G4,
|
|
TCG_REG_G5,
|
|
TCG_REG_G6,
|
|
TCG_REG_G7,
|
|
TCG_REG_O0,
|
|
TCG_REG_O1,
|
|
TCG_REG_O2,
|
|
TCG_REG_O3,
|
|
TCG_REG_O4,
|
|
TCG_REG_O5,
|
|
TCG_REG_O6,
|
|
TCG_REG_O7,
|
|
TCG_REG_L0,
|
|
TCG_REG_L1,
|
|
TCG_REG_L2,
|
|
TCG_REG_L3,
|
|
TCG_REG_L4,
|
|
TCG_REG_L5,
|
|
TCG_REG_L6,
|
|
TCG_REG_L7,
|
|
TCG_REG_I0,
|
|
TCG_REG_I1,
|
|
TCG_REG_I2,
|
|
TCG_REG_I3,
|
|
TCG_REG_I4,
|
|
TCG_REG_I5,
|
|
TCG_REG_I6,
|
|
TCG_REG_I7,
|
|
} TCGReg;
|
|
|
|
#define TCG_CT_CONST_S11 0x100
|
|
#define TCG_CT_CONST_S13 0x200
|
|
#define TCG_CT_CONST_ZERO 0x400
|
|
|
|
/* used for function call generation */
|
|
#define TCG_REG_CALL_STACK TCG_REG_O6
|
|
|
|
#ifdef __arch64__
|
|
#define TCG_TARGET_STACK_BIAS 2047
|
|
#define TCG_TARGET_STACK_ALIGN 16
|
|
#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS)
|
|
#else
|
|
#define TCG_TARGET_STACK_BIAS 0
|
|
#define TCG_TARGET_STACK_ALIGN 8
|
|
#define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4)
|
|
#endif
|
|
|
|
#ifdef __arch64__
|
|
#define TCG_TARGET_EXTEND_ARGS 1
|
|
#endif
|
|
|
|
#if defined(__VIS__) && __VIS__ >= 0x300
|
|
#define use_vis3_instructions 1
|
|
#else
|
|
extern bool use_vis3_instructions;
|
|
#endif
|
|
|
|
/* optional instructions */
|
|
#define TCG_TARGET_HAS_div_i32 1
|
|
#define TCG_TARGET_HAS_rem_i32 0
|
|
#define TCG_TARGET_HAS_rot_i32 0
|
|
#define TCG_TARGET_HAS_ext8s_i32 0
|
|
#define TCG_TARGET_HAS_ext16s_i32 0
|
|
#define TCG_TARGET_HAS_ext8u_i32 0
|
|
#define TCG_TARGET_HAS_ext16u_i32 0
|
|
#define TCG_TARGET_HAS_bswap16_i32 0
|
|
#define TCG_TARGET_HAS_bswap32_i32 0
|
|
#define TCG_TARGET_HAS_neg_i32 1
|
|
#define TCG_TARGET_HAS_not_i32 1
|
|
#define TCG_TARGET_HAS_andc_i32 1
|
|
#define TCG_TARGET_HAS_orc_i32 1
|
|
#define TCG_TARGET_HAS_eqv_i32 0
|
|
#define TCG_TARGET_HAS_nand_i32 0
|
|
#define TCG_TARGET_HAS_nor_i32 0
|
|
#define TCG_TARGET_HAS_clz_i32 0
|
|
#define TCG_TARGET_HAS_ctz_i32 0
|
|
#define TCG_TARGET_HAS_deposit_i32 0
|
|
#define TCG_TARGET_HAS_extract_i32 0
|
|
#define TCG_TARGET_HAS_sextract_i32 0
|
|
#define TCG_TARGET_HAS_movcond_i32 1
|
|
#define TCG_TARGET_HAS_add2_i32 1
|
|
#define TCG_TARGET_HAS_sub2_i32 1
|
|
#define TCG_TARGET_HAS_mulu2_i32 1
|
|
#define TCG_TARGET_HAS_muls2_i32 1
|
|
#define TCG_TARGET_HAS_muluh_i32 0
|
|
#define TCG_TARGET_HAS_mulsh_i32 0
|
|
|
|
#define TCG_TARGET_HAS_extrl_i64_i32 1
|
|
#define TCG_TARGET_HAS_extrh_i64_i32 1
|
|
#define TCG_TARGET_HAS_div_i64 1
|
|
#define TCG_TARGET_HAS_rem_i64 0
|
|
#define TCG_TARGET_HAS_rot_i64 0
|
|
#define TCG_TARGET_HAS_ext8s_i64 0
|
|
#define TCG_TARGET_HAS_ext16s_i64 0
|
|
#define TCG_TARGET_HAS_ext32s_i64 1
|
|
#define TCG_TARGET_HAS_ext8u_i64 0
|
|
#define TCG_TARGET_HAS_ext16u_i64 0
|
|
#define TCG_TARGET_HAS_ext32u_i64 1
|
|
#define TCG_TARGET_HAS_bswap16_i64 0
|
|
#define TCG_TARGET_HAS_bswap32_i64 0
|
|
#define TCG_TARGET_HAS_bswap64_i64 0
|
|
#define TCG_TARGET_HAS_neg_i64 1
|
|
#define TCG_TARGET_HAS_not_i64 1
|
|
#define TCG_TARGET_HAS_andc_i64 1
|
|
#define TCG_TARGET_HAS_orc_i64 1
|
|
#define TCG_TARGET_HAS_eqv_i64 0
|
|
#define TCG_TARGET_HAS_nand_i64 0
|
|
#define TCG_TARGET_HAS_nor_i64 0
|
|
#define TCG_TARGET_HAS_clz_i64 0
|
|
#define TCG_TARGET_HAS_ctz_i64 0
|
|
#define TCG_TARGET_HAS_deposit_i64 0
|
|
#define TCG_TARGET_HAS_extract_i64 0
|
|
#define TCG_TARGET_HAS_sextract_i64 0
|
|
#define TCG_TARGET_HAS_movcond_i64 1
|
|
#define TCG_TARGET_HAS_add2_i64 1
|
|
#define TCG_TARGET_HAS_sub2_i64 1
|
|
#define TCG_TARGET_HAS_mulu2_i64 0
|
|
#define TCG_TARGET_HAS_muls2_i64 0
|
|
#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions
|
|
#define TCG_TARGET_HAS_mulsh_i64 0
|
|
|
|
#define TCG_AREG0 TCG_REG_I0
|
|
|
|
#ifdef _MSC_VER
|
|
#include <windows.h>
|
|
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
|
|
{
|
|
FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start);
|
|
}
|
|
#else
|
|
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
|
|
{
|
|
uintptr_t p;
|
|
for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
|
|
__asm__ __volatile__("flush\t%0" : : "r" (p));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif
|