mirror of
https://github.com/yuzu-emu/unicorn
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232632e76c
This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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/* internal defines */
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typedef struct DisasContext {
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target_ulong pc;
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uint32_t insn;
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int is_jmp;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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TCGLabel *condlabel;
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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int thumb;
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int bswap_code;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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int vec_len;
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int vec_stride;
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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int aarch64;
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int current_el;
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GHashTable *cp_regs;
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uint64_t features; /* CPU features bits */
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/* Because unallocated encodings generate different exception syndrome
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* information from traps due to FP being disabled, we can't do a single
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* "is fp access disabled" check at a high level in the decode tree.
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* To help in catching bugs where the access check was forgotten in some
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* code path, we set this flag when the access check is done, and assert
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* that it is set at the point where we actually touch the FP regs.
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*/
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bool fp_access_checked;
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/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
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* single-step support).
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*/
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bool ss_active;
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bool pstate_ss;
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/* True if the insn just emitted was a load-exclusive instruction
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* (necessary for syndrome information for single step exceptions),
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if a single-step exception will be taken to the current EL */
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bool ss_same_el;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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// Unicorn engine
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struct uc_struct *uc;
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} DisasContext;
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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static inline int get_mem_index(DisasContext *s)
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{
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return s->current_el;
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}
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/* target-specific extra values for is_jmp */
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI 4
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#define DISAS_SWI 5
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/* For instructions which unconditionally cause an exception we can skip
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* emitting unreachable code at the end of the TB in the A64 decoder
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*/
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#define DISAS_EXC 6
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/* WFE */
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#define DISAS_WFE 7
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#define DISAS_HVC 8
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#define DISAS_SMC 9
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#ifdef TARGET_AARCH64
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void a64_translate_init(struct uc_struct *uc);
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void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc);
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void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
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#else
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static inline void a64_translate_init(struct uc_struct *uc)
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{
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}
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static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc)
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{
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}
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static inline void gen_a64_set_pc_im(uint64_t val)
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{
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}
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#endif
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void arm_gen_test_cc(TCGContext *tcg_ctx, int cc, TCGLabel *label);
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#endif /* TARGET_ARM_TRANSLATE_H */
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